Updated travis to run regression task
This commit is contained in:
Ganesh Gore
parent
e51ff44710
commit
2f0acfad23
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@ -1,50 +0,0 @@
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#!/bin/bash
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# Regression test version 1.0
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# Set variables
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my_pwd=$PWD
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fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
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vpr_path=${my_pwd}/vpr7_x2p/vpr
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benchmark="test_modes"
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include_netlists="_include_netlists.v"
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compiled_file="compiled_$benchmark"
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tb_formal_postfix="_top_formal_verification_random_tb"
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verilog_output_dirname="${benchmark}_Verilog"
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log_file="${benchmark}_sim.log"
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new_reg_sh="my_regression.sh"
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh -o $vpr_path/$new_reg_sh
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cd $my_pwd
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# Move to vpr folder
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cd $vpr_path
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# Remove former log file
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rm -f $log_file
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rm -f $compiled_file
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# Start the script -> run the fpga generation -> run the simulation -> check the log file
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source $new_reg_sh
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iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
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vvp $compiled_file -j 16 >> $log_file
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result=`grep "Succeed" $log_file`
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if ["$result" = ""]; then
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result=`grep "Failed" $log_file`
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if ["$result" = ""]; then
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echo "Unexpected error, Verification didn't run"
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cd $my_pwd
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exit 1
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else
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echo "Verification failed"
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cd $my_pwd
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exit 2
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fi
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else
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echo "Verification succeed"
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cd $my_pwd
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fi
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@ -26,4 +26,4 @@ end_section "OpenFPGA.build"
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$SPACER
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cd -
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python3.5 ./openfpga_flow/scripts/run_fpga_task.py basic_flow
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python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick
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@ -0,0 +1,2 @@
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arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem
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k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1
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@ -0,0 +1,38 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_22nm/22nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v
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[SYNTHESIS_PARAM]
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bench0_top = s298
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bench1_top = alu4
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bench2_top = tseng
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[SCRIPT_PARAM]
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min_route_chan_width=1.3
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end_flow_with_test=
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vpr_fpga_verilog_include_icarus_simulator=
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vpr_fpga_verilog_formal_verification_top_netlist=
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vpr_fpga_verilog_include_timing=
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vpr_fpga_verilog_include_signal_init=
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vpr_fpga_verilog_print_autocheck_top_testbench=
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[POST_RUN]
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