From 2f0acfad23c938db68feb3d147573d4705a17a32 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 21 Aug 2019 11:09:53 -0600 Subject: [PATCH] Updated travis to run regression task --- .travis/regression.sh | 50 ------------------- .travis/script.sh | 2 +- .../config/golden_results.txt | 2 + .../regression_quick/config/task.conf | 38 ++++++++++++++ 4 files changed, 41 insertions(+), 51 deletions(-) delete mode 100755 .travis/regression.sh create mode 100644 openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt create mode 100644 openfpga_flow/tasks/regression/regression_quick/config/task.conf diff --git a/.travis/regression.sh b/.travis/regression.sh deleted file mode 100755 index 5d9be167d..000000000 --- a/.travis/regression.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/bash -# Regression test version 1.0 - -# Set variables -my_pwd=$PWD -fpga_flow_scripts=${my_pwd}/fpga_flow/scripts -vpr_path=${my_pwd}/vpr7_x2p/vpr -benchmark="test_modes" -include_netlists="_include_netlists.v" -compiled_file="compiled_$benchmark" -tb_formal_postfix="_top_formal_verification_random_tb" -verilog_output_dirname="${benchmark}_Verilog" -log_file="${benchmark}_sim.log" -new_reg_sh="my_regression.sh" - - -cd $fpga_flow_scripts - -perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh -o $vpr_path/$new_reg_sh - -cd $my_pwd - -# Move to vpr folder -cd $vpr_path - -# Remove former log file -rm -f $log_file -rm -f $compiled_file - -# Start the script -> run the fpga generation -> run the simulation -> check the log file -source $new_reg_sh -iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix -vvp $compiled_file -j 16 >> $log_file - -result=`grep "Succeed" $log_file` -if ["$result" = ""]; then - result=`grep "Failed" $log_file` - if ["$result" = ""]; then - echo "Unexpected error, Verification didn't run" - cd $my_pwd - exit 1 - else - echo "Verification failed" - cd $my_pwd - exit 2 - fi -else - echo "Verification succeed" - cd $my_pwd -fi diff --git a/.travis/script.sh b/.travis/script.sh index 18845748b..e0c463239 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -26,4 +26,4 @@ end_section "OpenFPGA.build" $SPACER cd - -python3.5 ./openfpga_flow/scripts/run_fpga_task.py basic_flow +python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick diff --git a/openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt b/openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt new file mode 100644 index 000000000..edde206c7 --- /dev/null +++ b/openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1 diff --git a/openfpga_flow/tasks/regression/regression_quick/config/task.conf b/openfpga_flow/tasks/regression/regression_quick/config/task.conf new file mode 100644 index 000000000..277a3b6b7 --- /dev/null +++ b/openfpga_flow/tasks/regression/regression_quick/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_22nm/22nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v + +[SYNTHESIS_PARAM] +bench0_top = s298 +bench1_top = alu4 +bench2_top = tseng + +[SCRIPT_PARAM] +min_route_chan_width=1.3 +end_flow_with_test= +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= + +[POST_RUN] \ No newline at end of file