Changed yosys output file name
This commit is contained in:
Ganesh Gore
parent
8d0153d34e
commit
53941eaf5c
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@ -363,7 +363,7 @@ def run_yosys_with_abc():
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for eachfile in args.benchmark_files]),
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"TOP_MODULE": args.top_module,
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"LUT_SIZE": lut_size,
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"OUTPUT_BLIF": args.top_module+".blif",
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"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
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}
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yosys_template = os.path.join(
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cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
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@ -401,7 +401,7 @@ def run_abc_for_standarad():
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def run_ace2():
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if args.black_box_ace:
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with open(args.top_module+'.blif', 'r') as fp:
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with open(args.top_module+'_yosys_out.blif', 'r') as fp:
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blif_lines = fp.readlines()
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with open(args.top_module+'_bb.blif', 'w') as fp:
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@ -431,7 +431,8 @@ def run_ace2():
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fp.write(model_tmpl)
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# Prepare ACE run command
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command = [
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"-b", args.top_module+('_bb.blif' if args.black_box_ace else ".blif"),
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"-b", args.top_module +
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('_bb.blif' if args.black_box_ace else "_yosys_out.blif"),
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"-o", args.top_module+"_ace_out.act",
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"-n", args.top_module+"_ace_out.blif",
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"-c", "clk",
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@ -459,8 +460,8 @@ def run_ace2():
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def run_pro_blif_3arg():
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command = [
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"-i", args.top_module+"_ace_out.blif",
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"-o", args.top_module+"_ace_corrected_out.blif",
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"-initial_blif", args.top_module+'.blif',
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"-o", args.top_module+".blif",
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"-initial_blif", args.top_module+'_yosys_out.blif',
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]
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try:
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filename = args.top_module+'_blif_3args_output.txt'
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@ -484,7 +485,7 @@ def run_pro_blif_3arg():
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def run_vpr():
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# Run Standard VPR Flow
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min_channel_width = run_standard_vpr(
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args.top_module+"_ace_corrected_out.blif",
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args.top_module+".blif",
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-1,
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args.top_module+"_min_chan_width_vpr.txt")
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logger.info("Standard VPR flow routed with minimum %d Channels" %
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@ -499,7 +500,7 @@ def run_vpr():
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" (Slack of %d%%)" % ((args.min_route_chan_width-1)*100))
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while(1):
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res = run_standard_vpr(args.top_module+"_ace_corrected_out.blif",
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res = run_standard_vpr(args.top_module+".blif",
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int(min_channel_width),
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args.top_module+"_reroute_vpr.txt",
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route_only=True)
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@ -516,12 +517,12 @@ def run_vpr():
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min_channel_width)
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min_channel_width += 2
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extract_vpr_stats(args.top_module+"_min_channel_reroute_vpr.txt")
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extract_vpr_stats(args.top_module+"_reroute_vpr.txt")
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# Fixed routing channel width
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elif args.fix_route_chan_width:
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min_channel_width = run_standard_vpr(
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args.top_module+"_ace_corrected_out.blif",
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args.top_module+".blif",
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args.fix_route_chan_width,
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args.top_module+"_fr_chan_width.txt")
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logger.info("Fixed routing channel successfully routed with %d width" %
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@ -530,7 +531,9 @@ def run_vpr():
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else:
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extract_vpr_stats(args.top_module+"_min_chan_width.txt")
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if args.power:
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extract_vpr_power_esti(args.top_module+"_ace_corrected_out.power")
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extract_vpr_stats(logfile=args.top_module+".power",
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r_filename="vpr_power_stat",
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parse_section="power")
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def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
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@ -701,7 +704,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
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mult = 1
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extract_val = float(match.group(1))*mult
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else:
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extract_val = match.group(1)
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extract_val = match.group(1)
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except:
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logger.exception("Filter failed")
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extract_val= "Filter Failed"
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@ -719,7 +722,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
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def run_rewrite_verilog():
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# Rewrite the verilog after optimization
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script_cmd = [
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"read_blif %s" % args.top_module+"_ace_corrected_out.blif",
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"read_blif %s" % args.top_module+".blif",
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"write_verilog %s" % args.top_module+"_output_verilog.v"
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]
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command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
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@ -749,7 +752,7 @@ def run_netlists_verification():
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command = [cad_tools["iverilog_path"]]
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command += ["-o", compiled_file]
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command += ["./SRC/%s_ace_corrected_out_include_netlists.v" %
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command += ["./SRC/%s_include_netlists.v" %
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args.top_module]
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command += ["-s"]
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if args.vpr_fpga_verilog_formal_verification_top_netlist:
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@ -759,7 +762,11 @@ def run_netlists_verification():
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run_command("iverilog_verification", "iverilog_output.txt", command)
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vvp_command = ["vvp", compiled_file]
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run_command("vvp_verification", "vvp_sim_output.txt", vvp_command)
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output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command)
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if "Succeed" in output:
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logger.info("VVP Simulation Successful")
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else:
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logger.info(str(output).split("\n")[-1])
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def run_command(taskname, logfile, command, exit_if_fail=True):
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@ -780,7 +787,9 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
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process_failed_vpr_run(e.output)
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if exit_if_fail:
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clean_up_and_exit("Failed to run %s task" % taskname)
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return None
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logger.info("%s is written in file %s" % (taskname, logfile))
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return process.stdout
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def process_failed_vpr_run(vpr_output):
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45
run_test.sh
45
run_test.sh
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@ -1,43 +1,16 @@
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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./openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml \
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./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
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./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
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--top_module s298 \
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--power \
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--power_tech ./openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml \
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--power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \
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--min_route_chan_width 1.3 \
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--vpr_fpga_verilog \
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--vpr_fpga_verilog_dir ./SRC \
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--vpr_fpga_verilog_dir . \
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--vpr_fpga_x2p_rename_illegal_port \
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--vpr_fpga_verilog_print_autocheck_top_testbench
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# \
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# --end_flow_with_test \
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# --vpr_fpga_verilog_print_autocheck_top_testbench \
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# --vpr_fpga_verilog_include_icarus_simulator \
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# --vpr_fpga_verilog_formal_verification_top_netlist
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/vpr',
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/tmp/arch/k6_N10_rram_memory_bank_SC_winbond90.xml', 's298_ace_corrected_out.blif'
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# '--net_file'
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# 's298_vpr.net'
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# '--place_file'
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# 's298_vpr.place'
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# '--route_file'
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# 's298_vpr.route'
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# '--full_stats'
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# '--nodisp'
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# '--power'
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# '--activity_file'
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# 's298_ace_out.act'
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# '--tech_properties'
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml'
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# '--fpga_verilog'
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# '--fpga_verilog_dir'
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# './SRC'
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# '--fpga_verilog_print_autocheck_top_testbench'
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# 's298_output_verilog.v'
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# '--fpga_verilog_print_formal_verification_top_netlist'
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# '--fpga_verilog_include_icarus_simulator'
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# '--fpga_x2p_rename_illegal_port'
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--end_flow_with_test \
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--vpr_fpga_verilog_include_icarus_simulator \
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--vpr_fpga_verilog_formal_verification_top_netlist \
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--vpr_fpga_verilog_include_timing \
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--vpr_fpga_verilog_include_signal_init \
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--vpr_fpga_verilog_print_autocheck_top_testbench
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