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update regression tests

This commit is contained in:
tangxifan 2019-08-26 21:00:15 -06:00
parent 38e1d1bbff
commit de8a6bc833
3 changed files with 17 additions and 150 deletions
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3
.travis/script.sh
View File

@ -29,5 +29,4 @@ $SPACER
cd -
# python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick
chmod 755 run_test.sh
python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 6

31
openfpga_flow/tasks/blif_vpr_flow/config/task.conf
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@ -18,6 +18,7 @@ fpga_flow=vpr_blif
# arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
@ -28,7 +29,7 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_mode
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
bench0_chan_width = 300
[SCRIPT_PARAM_1]
[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
fix_route_chan_width=300
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
@ -44,17 +45,17 @@ vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=
# [SCRIPT_PARAM_2]
# fix_route_chan_width=200
# vpr_fpga_verilog_include_icarus_simulator=
# vpr_fpga_verilog_formal_verification_top_netlist=
# vpr_fpga_verilog_include_timing=
# vpr_fpga_verilog_include_signal_init=
# vpr_fpga_verilog_print_autocheck_top_testbench=
# vpr_fpga_bitstream_generator=
# vpr_fpga_verilog_print_user_defined_template=
# vpr_fpga_verilog_print_report_timing_tcl=
# vpr_fpga_verilog_print_sdc_pnr=
# vpr_fpga_verilog_print_sdc_analysis=
# vpr_fpga_x2p_compact_routing_hierarchy=
# end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=

133
run_test.sh
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@ -1,133 +0,0 @@
# python3.5 openfpga_flow/scripts/run_fpga_flow.py \
# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
# ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
# --top_module s298 \
# --power \
# --power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \
# --min_route_chan_width 1.3 \
# --vpr_fpga_verilog \
# --vpr_fpga_verilog_dir . \
# --vpr_fpga_x2p_rename_illegal_port \
# --end_flow_with_test \
# --vpr_fpga_verilog_include_icarus_simulator \
# --vpr_fpga_verilog_formal_verification_top_netlist \
# --vpr_fpga_verilog_include_timing \
# --vpr_fpga_verilog_include_signal_init \
# --vpr_fpga_verilog_print_autocheck_top_testbench
# Test popular multi-mode architecture
python3.5 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
--fpga_flow vpr_blif \
--top_module test_modes \
--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
#--fix_route_chan_width 300 \
--min_route_chan_width 1.3 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \
--vpr_fpga_verilog_include_icarus_simulator \
--vpr_fpga_verilog_formal_verification_top_netlist \
--vpr_fpga_verilog_include_timing \
--vpr_fpga_verilog_include_signal_init \
--vpr_fpga_verilog_print_autocheck_top_testbench \
--debug \
--vpr_fpga_bitstream_generator \
--vpr_fpga_verilog_print_user_defined_template \
--vpr_fpga_verilog_print_report_timing_tcl \
--vpr_fpga_verilog_print_sdc_pnr \
--vpr_fpga_verilog_print_sdc_analysis \
--vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
# Test Standard cell MUX2
python3.5 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
--fpga_flow vpr_blif \
--top_module test_modes \
--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
#--fix_route_chan_width 300 \
--min_route_chan_width 1.3 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \
--vpr_fpga_verilog_include_icarus_simulator \
--vpr_fpga_verilog_formal_verification_top_netlist \
--vpr_fpga_verilog_include_timing \
--vpr_fpga_verilog_include_signal_init \
--vpr_fpga_verilog_print_autocheck_top_testbench \
--debug \
--vpr_fpga_bitstream_generator \
--vpr_fpga_verilog_print_user_defined_template \
--vpr_fpga_verilog_print_report_timing_tcl \
--vpr_fpga_verilog_print_sdc_pnr \
--vpr_fpga_verilog_print_sdc_analysis \
--vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
# Test local encoder feature
python3.5 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
--fpga_flow vpr_blif \
--top_module test_modes \
--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
--fix_route_chan_width 300 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \
--vpr_fpga_verilog_include_icarus_simulator \
--vpr_fpga_verilog_formal_verification_top_netlist \
--vpr_fpga_verilog_include_timing \
--vpr_fpga_verilog_include_signal_init \
--vpr_fpga_verilog_print_autocheck_top_testbench \
--debug \
--vpr_fpga_bitstream_generator \
--vpr_fpga_verilog_print_user_defined_template \
--vpr_fpga_verilog_print_report_timing_tcl \
--vpr_fpga_verilog_print_sdc_pnr \
--vpr_fpga_verilog_print_sdc_analysis \
--vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
# Test tileable routing feature
#python3.5 openfpga_flow/scripts/run_fpga_flow.py \
#./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \
#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
#--fpga_flow vpr_blif \
#--top_module test_modes \
#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
#--power \
#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
##--fix_route_chan_width 300 \
#--min_route_chan_width 1.3 \
#--vpr_fpga_verilog \
#--vpr_fpga_verilog_dir . \
#--vpr_fpga_x2p_rename_illegal_port \
#--vpr_fpga_verilog_include_icarus_simulator \
#--vpr_fpga_verilog_formal_verification_top_netlist \
#--vpr_fpga_verilog_include_timing \
#--vpr_fpga_verilog_include_signal_init \
#--vpr_fpga_verilog_print_autocheck_top_testbench \
#--debug \
#--vpr_fpga_bitstream_generator \
#--vpr_fpga_verilog_print_user_defined_template \
#--vpr_fpga_verilog_print_report_timing_tcl \
#--vpr_fpga_verilog_print_sdc_pnr \
#--vpr_fpga_verilog_print_sdc_analysis \
#--vpr_fpga_x2p_compact_routing_hierarchy \
#--vpr_use_tileable_route_chan_width \
#--end_flow_with_test