Merge remote-tracking branch 'origin/ganesh_dev' into dev
This commit is contained in:
Ganesh Gore
commit
38e1d1bbff
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@ -10,10 +10,10 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
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#make
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mkdir build
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cd build
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cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
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cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
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make -j16
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alias python3.5="python3"
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ln -s /opt/local/bin/python3 /opt/loca/bin/python3.5
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ln -s /opt/local/bin/python3 /opt/local/bin/python3.5
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else
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# For linux, we enable full package compilation
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#make
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@ -30,4 +30,4 @@ $SPACER
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cd -
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# python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick
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chmod 755 run_test.sh
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./run_test.sh
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python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
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@ -0,0 +1 @@
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_build/
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@ -28,7 +28,7 @@ placement_time = "Placement took ([0-9.]+) seconds", str
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routing_time = "Routing took ([0-9.]+) seconds", str
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average_net_length = "average net length: ([0-9.]+)", str
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critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific
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total_time_taken = "Routing took ([0-9.]+) seconds", float
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total_routing_time = "Routing took ([0-9.]+) seconds", float
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[DEFAULT_PARSE_RESULT_POWER]
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pb_type_power="PB Types\s+([0-9]+)", str
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@ -535,10 +535,23 @@ def run_pro_blif_3arg():
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def collect_files_for_vpr():
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# Sanitize provided Benchmark option
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if len(args.benchmark_files) > 1:
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logger.error("Expecting Single Benchmark BLif file.")
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if not os.path.isfile(args.benchmark_files[0] or ""):
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clean_up_and_exit("Provided Blif file not found")
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shutil.copy(args.benchmark_files[0], args.top_module+".blif")
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# Sanitize provided Activity file option
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if not os.path.isfile(args.activity_file or ""):
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logger.error("Activity File - %s" % args.activity_file)
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clean_up_and_exit("Provided activity file not found")
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shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
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# Sanitize provided Benchmark option
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if not os.path.isfile(args.base_verilog or ""):
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logger.error("Base Verilog File - %s" % args.base_verilog)
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clean_up_and_exit("Provided base_verilog file not found")
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shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
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@ -1,4 +1,5 @@
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[GENERAL CONFIGURATION]
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task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks
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misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc
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python_path=python3.5
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script_default=${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py
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@ -12,9 +12,9 @@ import subprocess
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import threading
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import csv
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from string import Template
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import run_fpga_flow
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import pprint
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from importlib import util
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from collections import OrderedDict
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if util.find_spec("humanize"):
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import humanize
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@ -23,7 +23,7 @@ if util.find_spec("humanize"):
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# Configure logging system
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s (%(threadName)-9s) - %(message)s')
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format='%(levelname)s (%(threadName)10s) - %(message)s')
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logger = logging.getLogger('OpenFPGA_Task_logs')
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@ -71,7 +71,7 @@ def main():
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else:
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pprint.pprint(job_run_list)
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logger.info("Task execution completed")
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exit()
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exit(0)
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Subroutines starts here
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|
@ -80,8 +80,8 @@ def main():
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def clean_up_and_exit(msg):
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logger.error(msg)
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logger.error("Existing . . . . . .")
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exit()
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logger.error("Exiting . . . . . .")
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exit(1)
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def validate_command_line_arguments():
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@ -112,8 +112,8 @@ def generate_each_task_actions(taskname):
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curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1)
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try:
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os.mkdir(curr_run_dir)
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if os.path.islink('latest'):
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os.unlink("latest")
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if os.path.islink('latest') or os.path.exists('latest'):
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os.remove("latest")
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os.symlink(curr_run_dir, "latest")
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logger.info('Created "%s" directory for current task run' %
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curr_run_dir)
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@ -128,12 +128,17 @@ def generate_each_task_actions(taskname):
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task_conf.read_dict(script_env_vars)
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task_conf.read_file(open(curr_task_conf_file))
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required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"]
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required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES"]
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missing_section = list(set(required_sec)-set(task_conf.sections()))
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if missing_section:
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clean_up_and_exit("Missing sections %s" % " ".join(missing_section) +
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" in task configuration file")
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# Declare varibles to access sections
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TaskFileSections = task_conf.sections()
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SynthSection = task_conf["SYNTHESIS_PARAM"]
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GeneralSection = task_conf["GENERAL"]
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# Check if specified architecture files exist
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archfile_list = []
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for _, arch_file in task_conf["ARCHITECTURES"].items():
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@ -143,10 +148,16 @@ def generate_each_task_actions(taskname):
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else:
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clean_up_and_exit("Architecture file not found: " +
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"%s " % arch_file)
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if not len(archfile_list) == len(list(set(archfile_list))):
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clean_up_and_exit("Found duplicate architectures in config file")
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||||
# Check if specified benchmark files exist
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||||
benchmark_list = []
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for bech_name, each_benchmark in task_conf["BENCHMARKS"].items():
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# Declare varible to store paramteres for current benchmark
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CurrBenchPara = {}
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# Parse benchmark file
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bench_files = []
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for eachpath in each_benchmark.split(","):
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files = glob.glob(eachpath)
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@ -155,15 +166,51 @@ def generate_each_task_actions(taskname):
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" with path %s " % (eachpath))
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bench_files += files
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||||
ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common",
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fallback="")
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benchmark_list.append({
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||||
"files": bench_files,
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||||
"top_module": task_conf.get("SYNTHESIS_PARAM", bech_name+"_top",
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||||
fallback="top"),
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"ys_script": task_conf.get("SYNTHESIS_PARAM", bech_name+"_yosys",
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fallback=ys_for_task),
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||||
})
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||||
# Read provided benchmark configurations
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||||
# Common configurations
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||||
ys_for_task_common = SynthSection.get("bench_yosys_common")
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||||
chan_width_common = SynthSection.get("bench_chan_width_common")
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||||
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||||
# Individual benchmark configuration
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||||
CurrBenchPara["files"] = bench_files
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||||
CurrBenchPara["top_module"] = SynthSection.get(bech_name+"_top",
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||||
fallback="top")
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||||
CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys",
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||||
fallback=ys_for_task_common)
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||||
CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
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||||
fallback=chan_width_common)
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logger.info('Running "%s" flow' %
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GeneralSection.get("fpga_flow", fallback="yosys_vpr"))
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if GeneralSection.get("fpga_flow") == "vpr_blif":
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# Check if activity file exist
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||||
if not SynthSection.get(bech_name+"_act"):
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||||
clean_up_and_exit("Missing argument %s" % (bech_name+"_act") +
|
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"for vpr_blif flow")
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CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act")
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||||
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||||
# Check if base verilog file exists
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||||
if not SynthSection.get(bech_name+"_verilog"):
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||||
clean_up_and_exit("Missing argument %s for vpr_blif flow" %
|
||||
(bech_name+"_verilog"))
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||||
CurrBenchPara["verilog_file"] = SynthSection.get(
|
||||
bech_name+"_verilog")
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||||
|
||||
# Add script parameter list in current benchmark
|
||||
ScriptSections = [x for x in TaskFileSections if "SCRIPT_PARAM" in x]
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script_para_list = {}
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for eachset in ScriptSections:
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command = []
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for key, values in task_conf[eachset].items():
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||||
command += ["--"+key, values] if values else ["--"+key]
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||||
# Set label for Sript Parameters
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set_lbl = eachset.replace("SCRIPT_PARAM", "")
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||||
set_lbl = set_lbl[1:] if set_lbl else "Common"
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script_para_list[set_lbl] = command
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CurrBenchPara["script_params"] = script_para_list
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|
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benchmark_list.append(CurrBenchPara)
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# Create OpenFPGA flow run commnad for each combination of
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# architecture, benchmark and parameters
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|
@ -171,16 +218,21 @@ def generate_each_task_actions(taskname):
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flow_run_cmd_list = []
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for indx, arch in enumerate(archfile_list):
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for bench in benchmark_list:
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flow_run_dir = get_flow_rundir(arch, bench["top_module"])
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cmd = create_run_command(
|
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flow_run_dir, arch, bench, task_conf)
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flow_run_cmd_list.append({
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||||
"arch": arch,
|
||||
"bench": bench,
|
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"name": "%s_arch%d" % (bench["top_module"], indx),
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||||
"run_dir": flow_run_dir,
|
||||
"commands": cmd,
|
||||
"status": False})
|
||||
for lbl, param in bench["script_params"].items():
|
||||
flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl)
|
||||
command = create_run_command(
|
||||
curr_job_dir=flow_run_dir,
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archfile=arch,
|
||||
benchmark_obj=bench,
|
||||
param=param,
|
||||
task_conf=task_conf)
|
||||
flow_run_cmd_list.append({
|
||||
"arch": arch,
|
||||
"bench": bench,
|
||||
"name": "%02d_arch%s_%s" % (indx, bench["top_module"], lbl),
|
||||
"run_dir": flow_run_dir,
|
||||
"commands": command,
|
||||
"status": False})
|
||||
return flow_run_cmd_list
|
||||
|
||||
|
||||
|
|
@ -193,7 +245,7 @@ def get_flow_rundir(arch, top_module, flow_params=None):
|
|||
return os.path.abspath(os.path.join(*path))
|
||||
|
||||
|
||||
def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf):
|
||||
def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
|
||||
"""
|
||||
Create_run_script function accepts run directory, architecture list and
|
||||
fpga_flow configuration file and prepare final executable fpga_flow script
|
||||
|
|
@ -217,23 +269,37 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf):
|
|||
os.makedirs(curr_job_dir)
|
||||
|
||||
# Make execution command to run Open FPGA flow
|
||||
task_gc = task_conf["GENERAL"]
|
||||
command = [archfile] + benchmark_obj["files"]
|
||||
command += ["--top_module", benchmark_obj["top_module"]]
|
||||
command += ["--run_dir", curr_job_dir]
|
||||
if task_conf.getboolean("GENERAL", "power_analysis", fallback=False):
|
||||
|
||||
if task_gc.get("fpga_flow"):
|
||||
command += ["--fpga_flow", task_gc.get("fpga_flow")]
|
||||
|
||||
if benchmark_obj.get("activity_file"):
|
||||
command += ["--activity_file", benchmark_obj.get("activity_file")]
|
||||
|
||||
if benchmark_obj.get("verilog_file"):
|
||||
command += ["--base_verilog", benchmark_obj.get("verilog_file")]
|
||||
|
||||
if benchmark_obj.get("ys_script"):
|
||||
command += ["--yosys_tmpl", benchmark_obj["ys_script"]]
|
||||
|
||||
if task_gc.getboolean("power_analysis"):
|
||||
command += ["--power"]
|
||||
command += ["--power_tech",
|
||||
task_conf.get("GENERAL", "power_tech_file")]
|
||||
if task_conf.getboolean("GENERAL", "spice_output", fallback=False):
|
||||
command += ["--power_tech", task_gc.get("power_tech_file")]
|
||||
|
||||
if task_gc.getboolean("spice_output"):
|
||||
command += ["--vpr_fpga_spice"]
|
||||
if task_conf.getboolean("GENERAL", "verilog_output", fallback=False):
|
||||
|
||||
if task_gc.getboolean("verilog_output"):
|
||||
command += ["--vpr_fpga_verilog"]
|
||||
command += ["--vpr_fpga_verilog_dir", "."]
|
||||
command += ["--vpr_fpga_x2p_rename_illegal_port"]
|
||||
|
||||
# Add other paramters to pass
|
||||
for key, values in task_conf["SCRIPT_PARAM"].items():
|
||||
command += ["--"+key, values] if values else ["--"+key]
|
||||
command += param
|
||||
|
||||
if args.debug:
|
||||
command += ["--debug"]
|
||||
|
|
@ -260,9 +326,13 @@ def run_single_script(s, eachJob):
|
|||
try:
|
||||
logfile = "%s_out.log" % name
|
||||
with open(logfile, 'w+') as output:
|
||||
process = subprocess.Popen(["python3.5",
|
||||
gc["script_default"]] +
|
||||
eachJob["commands"],
|
||||
output.write("* "*20 + '\n')
|
||||
output.write("RunDirectory : %s\n" % os.getcwd())
|
||||
command = [gc["python_path"], gc["script_default"]] + \
|
||||
eachJob["commands"]
|
||||
output.write(" ".join(command) + '\n')
|
||||
output.write("* "*20 + '\n')
|
||||
process = subprocess.Popen(command,
|
||||
stdout=subprocess.PIPE,
|
||||
stderr=subprocess.STDOUT,
|
||||
universal_newlines=True)
|
||||
|
|
@ -272,6 +342,8 @@ def run_single_script(s, eachJob):
|
|||
sys.stdout.buffer.flush()
|
||||
output.write(line)
|
||||
process.wait()
|
||||
if process.returncode:
|
||||
raise subprocess.CalledProcessError(0, [])
|
||||
eachJob["status"] = True
|
||||
except:
|
||||
logger.exception("Failed to execute openfpga flow - " +
|
||||
|
|
@ -280,7 +352,8 @@ def run_single_script(s, eachJob):
|
|||
timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"]))
|
||||
timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \
|
||||
else str(timediff)
|
||||
logger.info("%s Finished, Time Taken %s " % (name, timestr))
|
||||
logger.info("%s Finished with returncode %d, Time Taken %s " %
|
||||
(name, process.returncode, timestr))
|
||||
|
||||
|
||||
def run_actions(job_run_list):
|
||||
|
|
@ -301,6 +374,7 @@ def collect_results(job_run_list):
|
|||
task_result = []
|
||||
for run in job_run_list:
|
||||
if not run["status"]:
|
||||
logger.warning("Skipping %s run", run["name"])
|
||||
continue
|
||||
# Check if any result file exist
|
||||
if not glob.glob(os.path.join(run["run_dir"], "*.result")):
|
||||
|
|
@ -311,8 +385,10 @@ def collect_results(job_run_list):
|
|||
interpolation=ExtendedInterpolation())
|
||||
vpr_res.read_file(
|
||||
open(os.path.join(run["run_dir"], "vpr_stat.result")))
|
||||
result = dict(vpr_res["RESULTS"])
|
||||
result = OrderedDict()
|
||||
result["name"] = run["name"]
|
||||
result["TotalRunTime"] = int(run["endtime"]-run["starttime"])
|
||||
result.update(vpr_res["RESULTS"])
|
||||
task_result.append(result)
|
||||
|
||||
if len(task_result):
|
||||
|
|
|
|||
|
|
@ -18,18 +18,17 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank
|
|||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v
|
||||
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys
|
||||
bench0_top = s298
|
||||
bench1_top = alu4
|
||||
bench2_top = s38417
|
||||
bench0_yosys=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys
|
||||
bench1_top = elliptic
|
||||
|
||||
[SCRIPT_PARAM]
|
||||
min_route_chan_width=30
|
||||
[SCRIPT_PARAM_1]
|
||||
min_route_chan_width=1.3
|
||||
|
||||
[SCRIPT_PARAM_2]
|
||||
min_route_chan_width=1.8
|
||||
|
||||
[POST_RUN]
|
||||
# Not Implemented yet
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
|
||||
[ARCHITECTURES]
|
||||
# arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
|
||||
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
|
||||
arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = test_modes
|
||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
|
||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
|
||||
bench0_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_1]
|
||||
fix_route_chan_width=300
|
||||
vpr_fpga_verilog_include_icarus_simulator=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
vpr_fpga_verilog_include_timing=
|
||||
vpr_fpga_verilog_include_signal_init=
|
||||
vpr_fpga_verilog_print_autocheck_top_testbench=
|
||||
vpr_fpga_bitstream_generator=
|
||||
vpr_fpga_verilog_print_user_defined_template=
|
||||
vpr_fpga_verilog_print_report_timing_tcl=
|
||||
vpr_fpga_verilog_print_sdc_pnr=
|
||||
vpr_fpga_verilog_print_sdc_analysis=
|
||||
vpr_fpga_x2p_compact_routing_hierarchy=
|
||||
end_flow_with_test=
|
||||
|
||||
|
||||
# [SCRIPT_PARAM_2]
|
||||
# fix_route_chan_width=200
|
||||
# vpr_fpga_verilog_include_icarus_simulator=
|
||||
# vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
# vpr_fpga_verilog_include_timing=
|
||||
# vpr_fpga_verilog_include_signal_init=
|
||||
# vpr_fpga_verilog_print_autocheck_top_testbench=
|
||||
# vpr_fpga_bitstream_generator=
|
||||
# vpr_fpga_verilog_print_user_defined_template=
|
||||
# vpr_fpga_verilog_print_report_timing_tcl=
|
||||
# vpr_fpga_verilog_print_sdc_pnr=
|
||||
# vpr_fpga_verilog_print_sdc_analysis=
|
||||
# vpr_fpga_x2p_compact_routing_hierarchy=
|
||||
# end_flow_with_test=
|
||||
Loading…
Reference in New Issue