Clifford Wolf
|
55521c085a
|
Fixed RTLIL code generator for part select of parameter
|
2014-07-28 15:31:19 +02:00 |
Clifford Wolf
|
0598bc8708
|
Fixed width detection for part selects
|
2014-07-28 15:19:34 +02:00 |
Clifford Wolf
|
27a872d1e7
|
Added support for "upto" wires to Verilog front- and back-end
|
2014-07-28 14:25:03 +02:00 |
Clifford Wolf
|
3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
|
2014-07-28 12:12:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
ee65dea738
|
Fixed signdness detection of expressions with bit- and part-selects
|
2014-07-28 10:10:08 +02:00 |
Clifford Wolf
|
c4bdba78cb
|
Added proper Design->addModule interface
|
2014-07-27 21:12:09 +02:00 |
Clifford Wolf
|
7661ded8dd
|
Fixed verific bindings for new RTLIL api
|
2014-07-27 12:00:28 +02:00 |
Clifford Wolf
|
6b34215efd
|
Fixed ilang parser for new RTLIL API
|
2014-07-27 11:56:35 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
97a59851a6
|
Added RTLIL::Cell::has(portname)
|
2014-07-26 16:11:28 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
309d64d46a
|
Fixed two memory leaks in ast simplify
|
2014-07-25 13:24:10 +02:00 |
Clifford Wolf
|
1488bc0c4f
|
Updated verific build/test instructions
|
2014-07-25 12:16:03 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
b17d6531c8
|
Added "make PRETTY=1"
|
2014-07-24 17:15:01 +02:00 |
Clifford Wolf
|
375aa71dfe
|
Various fixes in Verific frontend for new RTLIL API
|
2014-07-23 21:35:01 +02:00 |
Clifford Wolf
|
20a7965f61
|
Various small fixes (from gcc compiler warnings)
|
2014-07-23 20:45:27 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
ec923652e2
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
|
2014-07-23 09:52:55 +02:00 |
Clifford Wolf
|
a8d3a68971
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
|
2014-07-23 09:49:43 +02:00 |
Clifford Wolf
|
115dd959d9
|
SigSpec refactoring: More cleanups of old SigSpec use pattern
|
2014-07-22 23:50:21 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
7bffde6abd
|
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
|
2014-07-22 20:39:38 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
3b5f4ff39c
|
Fixed ilang parsing of process attributes
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
d6d0e08834
|
Fixed make rules for ilang parser
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
4147b55c23
|
Added "autoidx" statement to ilang file format
|
2014-07-21 15:15:18 +02:00 |
Clifford Wolf
|
361e0d62ff
|
Replaced depricated NEW_WIRE macro with module->addWire() calls
|
2014-07-21 12:42:02 +02:00 |
Clifford Wolf
|
1d88f1cf9f
|
Removed deprecated module->new_wire()
|
2014-07-21 12:35:06 +02:00 |
Clifford Wolf
|
9b183539af
|
Implemented dynamic bit-/part-select for memory writes
|
2014-07-17 16:49:23 +02:00 |
Clifford Wolf
|
5867f6bcdc
|
Added support for bit/part select to mem2reg rewriter
|
2014-07-17 13:49:32 +02:00 |
Clifford Wolf
|
6d69d4aaa8
|
Added support for constant bit- or part-select for memory writes
|
2014-07-17 13:13:21 +02:00 |
Clifford Wolf
|
b171a4c1bc
|
Added "inout" ports support to read_liberty
|
2014-07-16 18:12:46 +02:00 |
Clifford Wolf
|
5057935722
|
Set blackbox attribute in "read_liberty -lib"
|
2014-07-16 18:12:16 +02:00 |
Clifford Wolf
|
24f58e57f3
|
Fixed spelling of "direction" in read_liberty messages
|
2014-07-16 18:02:28 +02:00 |
Clifford Wolf
|
543551b80a
|
changes in verilog frontend for new $mem/$memwr WR_EN interface
|
2014-07-16 12:49:50 +02:00 |
Clifford Wolf
|
0f9ca49dc6
|
Added passing of various options to vhdl2verilog
|
2014-07-12 10:02:39 +02:00 |
Clifford Wolf
|
55a1b8dbac
|
Fixed processing of initial values for block-local variables
|
2014-07-11 13:05:53 +02:00 |
Clifford Wolf
|
ee8ad72fd9
|
fixed parsing of constant with comment between size and value
|
2014-07-02 06:27:04 +02:00 |
Clifford Wolf
|
076182c34e
|
Fixed handling of mixed real/int ternary expressions
|
2014-06-25 10:05:36 +02:00 |
Clifford Wolf
|
4fc43d1932
|
More found_real-related fixes to AstNode::detectSignWidthWorker
|
2014-06-24 15:08:48 +02:00 |
Clifford Wolf
|
65b2e9c064
|
fixed signdness detection for expressions with reals
|
2014-06-21 21:41:13 +02:00 |
Clifford Wolf
|
80e4594695
|
Added AstNode::MEM2REG_FL_CMPLX_LHS
|
2014-06-17 21:39:25 +02:00 |
Clifford Wolf
|
798ff88855
|
Improved handling of relational op of real values
|
2014-06-17 12:47:51 +02:00 |
Clifford Wolf
|
6c17d4f242
|
Improved ternary support for real values
|
2014-06-16 15:12:24 +02:00 |
Clifford Wolf
|
82bbd2f077
|
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
|
2014-06-16 15:05:37 +02:00 |
Clifford Wolf
|
0c4c79c4c6
|
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
|
2014-06-16 15:02:40 +02:00 |
Clifford Wolf
|
5bfe865cec
|
Added found_real feature to AstNode::detectSignWidth
|
2014-06-16 15:00:57 +02:00 |
Clifford Wolf
|
4d1df128fa
|
Improved AstNode::realAsConst for large numbers
|
2014-06-15 09:27:09 +02:00 |
Clifford Wolf
|
7f57bc8385
|
Improved parsing of large integer constants
|
2014-06-15 08:48:17 +02:00 |
Clifford Wolf
|
48dc6ab98d
|
Improved AstNode::asReal for large integers
|
2014-06-15 08:38:31 +02:00 |
Clifford Wolf
|
149fe83a8d
|
improved (fixed) conversion of real values to bit vectors
|
2014-06-14 21:00:51 +02:00 |
Clifford Wolf
|
d5765b5e14
|
Fixed relational operators for const real expressions
|
2014-06-14 19:33:58 +02:00 |
Clifford Wolf
|
f3b4a9dd24
|
Added support for math functions
|
2014-06-14 13:36:23 +02:00 |
Clifford Wolf
|
9bd7d5c468
|
Added handling of real-valued parameters/localparams
|
2014-06-14 12:00:47 +02:00 |
Clifford Wolf
|
fc7b6d172a
|
Implemented more real arithmetic
|
2014-06-14 11:27:05 +02:00 |
Clifford Wolf
|
442a8e2875
|
Implemented basic real arithmetic
|
2014-06-14 08:51:22 +02:00 |
Clifford Wolf
|
9dd16fa41c
|
Added real->int convertion in ast genrtlil
|
2014-06-14 07:44:19 +02:00 |
Clifford Wolf
|
7ef0da32cd
|
Added Verilog lexer and parser support for real values
|
2014-06-13 11:29:23 +02:00 |
Clifford Wolf
|
482d9208aa
|
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
|
2014-06-12 11:54:20 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
0b1ce63a19
|
Added support for repeat stmt in const functions
|
2014-06-07 10:47:53 +02:00 |
Clifford Wolf
|
7c8a7b2131
|
further improved const function support
|
2014-06-07 00:02:05 +02:00 |
Clifford Wolf
|
5281562d0e
|
made the generate..endgenrate keywords optional
|
2014-06-06 23:05:01 +02:00 |
Clifford Wolf
|
76da2fe172
|
improved const function support
|
2014-06-06 22:55:02 +02:00 |
Clifford Wolf
|
5c10d2ee36
|
fix functions with no block (but single statement, loop, etc.)
|
2014-06-06 21:29:23 +02:00 |
Clifford Wolf
|
ab54ce17c8
|
improved ast simplify of const functions
|
2014-06-06 17:40:45 +02:00 |
Clifford Wolf
|
b5cd7a0179
|
added while and repeat support to verilog parser
|
2014-06-06 17:40:04 +02:00 |
Clifford Wolf
|
f9c1cd5edb
|
Improved error message for options after front-end filename arguments
|
2014-06-04 09:10:50 +02:00 |
Johann Glaser
|
63dfbb18cf
|
new flags -ignore_miss_func and -ignore_miss_dir for read_liberty
|
2014-05-28 16:50:13 +02:00 |
Clifford Wolf
|
7188542155
|
Fixed clang -Wdeprecated-register warnings
|
2014-04-20 14:28:23 +02:00 |
Clifford Wolf
|
a1be4816d6
|
Replaced depricated %name-prefix= bison directive
|
2014-04-20 14:22:11 +02:00 |
Clifford Wolf
|
a3b9692a68
|
Fixed mapping of Verific WIDE_DFFRS operator
|
2014-03-20 13:40:01 +01:00 |
Clifford Wolf
|
470c2455e4
|
Fixed mapping of Verific FADD primitive with unconnected outputs
|
2014-03-20 13:26:52 +01:00 |
Clifford Wolf
|
cdf1257565
|
Progress in Verific bindings
|
2014-03-17 14:43:16 +01:00 |
Clifford Wolf
|
0b0dcfda7d
|
Progress in Verific bindings
|
2014-03-17 02:43:53 +01:00 |
Clifford Wolf
|
a67cd2d4a2
|
Progress in Verific bindings
|
2014-03-17 01:56:00 +01:00 |
Clifford Wolf
|
acda74c12c
|
Added support for memories to verific bindings
|
2014-03-16 17:05:05 +01:00 |
Clifford Wolf
|
7545510edc
|
Use Verific Net::{IsGnd,IsPwr} API in Verific bindings
|
2014-03-16 16:06:03 +01:00 |
Clifford Wolf
|
0ebee4c8e7
|
Progress in Verific bindings
|
2014-03-15 22:51:12 +01:00 |
Clifford Wolf
|
fc2c821407
|
Progress in Verific bindings
|
2014-03-15 15:31:54 +01:00 |
Clifford Wolf
|
1d00ad9d4d
|
Progress in Verific bindings
|
2014-03-15 14:36:11 +01:00 |
Clifford Wolf
|
e37d672ae7
|
Progress in Verific bindings
|
2014-03-14 16:40:25 +01:00 |
Clifford Wolf
|
0ac915a757
|
Progress in Verific bindings
|
2014-03-14 11:46:13 +01:00 |
Clifford Wolf
|
9a1accf692
|
Progress in Verific bindings
|
2014-03-13 18:21:00 +01:00 |
Clifford Wolf
|
6a53bc7b27
|
Copy Verific vdbs files to Yosys "share" data directory
|
2014-03-13 17:34:31 +01:00 |
Clifford Wolf
|
7a1ac11203
|
Added test_navre.ys for verific frontend
|
2014-03-13 13:12:06 +01:00 |
Clifford Wolf
|
fad8558eb5
|
Merged OSX fixes from Siesh1oo with some modifications
|
2014-03-13 12:48:10 +01:00 |
Clifford Wolf
|
91704a7853
|
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
|
2014-03-11 14:24:24 +01:00 |
Clifford Wolf
|
9992026a8d
|
Added support for `line compiler directive
|
2014-03-11 14:06:57 +01:00 |
Clifford Wolf
|
5a15539c9b
|
Improved verific command (added support for some operators)
|
2014-03-10 12:06:57 +01:00 |
Clifford Wolf
|
c71791a1ff
|
Improvements in verific command
|
2014-03-10 03:03:08 +01:00 |
Clifford Wolf
|
8d06f9f2fe
|
Added "verific" command
|
2014-03-09 20:40:04 +01:00 |
Clifford Wolf
|
620d51d9f7
|
Bugfix in ilang frontend autoidx recovery
|
2014-03-07 17:19:14 +01:00 |
Clifford Wolf
|
4d07f88258
|
Fixed gcc compiler warning
|
2014-03-06 16:37:19 +01:00 |
Clifford Wolf
|
09805ee9ec
|
Include id2ast pointers when dumping AST
|
2014-03-05 19:56:31 +01:00 |
Clifford Wolf
|
d6a01fe412
|
Fixed merging of compatible wire decls in AST frontend
|
2014-03-05 19:55:58 +01:00 |
Clifford Wolf
|
de7bd12004
|
Bugfix in recursive AST simplification
|
2014-03-05 19:45:33 +01:00 |
Clifford Wolf
|
ef90236a5d
|
Fixed vhdl2verilog temp dir name
|
2014-03-01 17:48:15 +01:00 |
Clifford Wolf
|
04999f4af0
|
Fixed vhdl2verilog help message
|
2014-03-01 17:47:19 +01:00 |
Clifford Wolf
|
ae5032af84
|
Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
|
2014-02-26 21:32:19 +01:00 |
Clifford Wolf
|
6bc94b7eb2
|
Don't blow up constants unneccessarily in Verilog frontend
|
2014-02-24 12:41:25 +01:00 |
Clifford Wolf
|
f8c9143b2b
|
Fixed bug in generation of undefs for $memwr MUXes
|
2014-02-22 17:08:00 +01:00 |
Clifford Wolf
|
0a60f95224
|
Added vhdl2verilog
|
2014-02-21 18:59:49 +01:00 |
Clifford Wolf
|
4bd25edcd4
|
Cleanups in handling of read_verilog -defer and -icells
|
2014-02-20 19:12:32 +01:00 |
Clifford Wolf
|
02e6f2c5be
|
Added Verilog support for "`default_nettype none"
|
2014-02-17 14:28:52 +01:00 |
Clifford Wolf
|
7d7e068dd1
|
Added a warning note about error reporting to read_verilog help message
|
2014-02-16 20:20:25 +01:00 |
Clifford Wolf
|
7ac524e8e8
|
Improved support for constant functions
|
2014-02-16 13:16:38 +01:00 |
Clifford Wolf
|
118517ca5a
|
Added ff and latch support to read_liberty
|
2014-02-15 19:44:19 +01:00 |
Clifford Wolf
|
96b1ebc8dc
|
Bugfix in expression parser of read_liberty
|
2014-02-15 19:36:09 +01:00 |
Clifford Wolf
|
5e39e6ece2
|
Correctly convert constants to RTLIL (fixed undef handling)
|
2014-02-15 15:42:10 +01:00 |
Clifford Wolf
|
4440610d3f
|
Added liberty frontend
|
2014-02-15 12:57:28 +01:00 |
Clifford Wolf
|
45d2b6ffce
|
Be more conservative with new const-function code
|
2014-02-14 20:45:30 +01:00 |
Clifford Wolf
|
e8af3def7f
|
Added support for FOR loops in function calls in parameters
|
2014-02-14 20:33:22 +01:00 |
Clifford Wolf
|
534c1a5dd0
|
Created basic support for function calls in parameter values
|
2014-02-14 19:56:44 +01:00 |
Clifford Wolf
|
cd9e8741a7
|
Implemented read_verilog -defer
|
2014-02-13 13:59:13 +01:00 |
Clifford Wolf
|
007bdff55d
|
Added support for functions returning integer
|
2014-02-12 23:29:54 +01:00 |
Clifford Wolf
|
0defc86519
|
renamed ilang "scope error" to "ilang error"
|
2014-02-11 19:17:07 +01:00 |
Clifford Wolf
|
fb186e6299
|
Improved ilang parser error messages
|
2014-02-09 15:35:31 +01:00 |
Clifford Wolf
|
f4f230d7cc
|
Fixed gcc compiler warnings with release build
|
2014-02-06 22:49:14 +01:00 |
Clifford Wolf
|
aa8e754ae5
|
Added read_verilog -setattr
|
2014-02-05 11:22:10 +01:00 |
Clifford Wolf
|
d267bcde4e
|
Fixed bug in sequential sat proofs and improved handling of asserts
|
2014-02-04 12:46:16 +01:00 |
Clifford Wolf
|
a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
|
2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
cdd6e11af5
|
Added support for blanks after -I and -D in read_verilog
|
2014-02-02 13:06:21 +01:00 |
Clifford Wolf
|
af325bf206
|
Fixed comment/eol parsing in ilang frontend
|
2014-02-01 17:28:02 +01:00 |
Clifford Wolf
|
d06258f74f
|
Added constant size expression support of sized constants
|
2014-02-01 13:50:23 +01:00 |
Clifford Wolf
|
4df7e03ec9
|
Bugfix in name resolution with generate blocks
|
2014-01-30 15:01:28 +01:00 |
Clifford Wolf
|
375c4dddc1
|
Added read_verilog -icells option
|
2014-01-29 00:59:28 +01:00 |
Clifford Wolf
|
0b47d907d3
|
Fixed handling of unsized constants in verilog frontend
|
2014-01-24 15:05:24 +01:00 |
Clifford Wolf
|
88fbdd4916
|
Fixed algorithmic complexity of AST simplification of long expressions
|
2014-01-20 20:25:20 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
9a1eb45c75
|
Added Verilog parser support for asserts
|
2014-01-19 04:18:22 +01:00 |
Clifford Wolf
|
13359d65ba
|
Fixed parsing of verilog macros at end of line
|
2014-01-18 19:22:20 +01:00 |
Clifford Wolf
|
6170cfe9cd
|
Added verilog_defaults command
|
2014-01-17 17:22:29 +01:00 |
Clifford Wolf
|
a3d94bf888
|
Fixed typo in frontends/ast/simplify.cc
|
2014-01-12 21:04:42 +01:00 |
Clifford Wolf
|
8f11eaaca6
|
Added updating of RTLIL::autoidx to ilang frontend
|
2014-01-03 17:51:05 +01:00 |
Clifford Wolf
|
fb2bf934dc
|
Added correct handling of $memwr priority
|
2014-01-03 00:22:17 +01:00 |
Clifford Wolf
|
364f277afb
|
Fixed a stupid access after delete bug
|
2013-12-29 20:18:22 +01:00 |
Clifford Wolf
|
1dcbba1abf
|
Fixed parsing of non-arg macro calls followed by "("
|
2013-12-27 16:25:27 +01:00 |
Clifford Wolf
|
72026a934e
|
Fixed parsing of macros with no arguments and expansion text starting with "("
|
2013-12-27 15:05:52 +01:00 |
Clifford Wolf
|
369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
fbd06a1afc
|
Added elsif preproc support
|
2013-12-18 13:41:36 +01:00 |
Clifford Wolf
|
921064c200
|
Added support for macro arguments
|
2013-12-18 13:21:02 +01:00 |
Clifford Wolf
|
891e4b5b0d
|
Keep strings as strings in const ternary and concat
|
2013-12-05 13:26:17 +01:00 |
Clifford Wolf
|
e935bb6eda
|
Added const folding support for $signed and $unsigned
|
2013-12-05 13:09:41 +01:00 |
Clifford Wolf
|
5c39948ead
|
Added AstNode::mkconst_str API
|
2013-12-05 12:53:49 +01:00 |
Clifford Wolf
|
853538d78b
|
Fixed generate-for (and disabled double warning for auto-wire)
|
2013-12-04 21:33:00 +01:00 |
Clifford Wolf
|
3c220e0b32
|
Added support for $clog2 system function
|
2013-12-04 21:19:54 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
10aa08dca1
|
Fixed temp net name generation in rtlil process generator for abbreviated name matching
|
2013-11-28 21:47:08 +01:00 |
Clifford Wolf
|
0e52f3fa01
|
Added "src" attribute to processes
|
2013-11-28 17:37:50 +01:00 |
Clifford Wolf
|
8dafecd34d
|
Added module->avail_parameters (for advanced techmap features)
|
2013-11-24 20:29:07 +01:00 |
Clifford Wolf
|
7d9a90396d
|
Added verilog frontend -ignore_redef option
|
2013-11-24 19:57:42 +01:00 |
Clifford Wolf
|
019b301541
|
Early wire/reg/parameter width calculation in ast/simplify
|
2013-11-24 19:40:23 +01:00 |
Clifford Wolf
|
0ef22c7609
|
Added support for signed parameters in ilang
|
2013-11-24 17:37:27 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
1de12e1efc
|
Improved handling of initialized registers
|
2013-11-23 16:26:59 +01:00 |
Clifford Wolf
|
295e352ba6
|
Renamed "placeholder" to "blackbox"
|
2013-11-22 15:01:12 +01:00 |
Clifford Wolf
|
a362fd81ae
|
Fixed O(n^2) performance bug in verilog preprocessor
|
2013-11-22 14:08:43 +01:00 |
Clifford Wolf
|
e4429c480e
|
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
|
2013-11-22 12:46:02 +01:00 |
Clifford Wolf
|
95c94a02fc
|
Fixed async proc detection in mem2reg
|
2013-11-21 21:26:56 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
08ceb3729e
|
Fixed ilang parser: memory width
|
2013-11-20 19:55:52 +01:00 |
Clifford Wolf
|
65ad556f3d
|
Another name resolution bugfix for generate blocks
|
2013-11-20 13:57:40 +01:00 |
Clifford Wolf
|
92035fb38e
|
Implemented indexed part selects
|
2013-11-20 13:05:27 +01:00 |
Clifford Wolf
|
c4c299eb5a
|
Do not allow memory bit select on the left side of an assignment
|
2013-11-20 12:18:46 +01:00 |
Clifford Wolf
|
0f04738f40
|
Added "synthesis" in (synopsys|synthesis) comment support
|
2013-11-20 11:44:09 +01:00 |
Clifford Wolf
|
ac2be2d892
|
Fixed name resolution of local tasks and functions in generate block
|
2013-11-20 11:05:58 +01:00 |
Clifford Wolf
|
19dba2561e
|
Implemented part/bit select on memory read
|
2013-11-20 10:51:32 +01:00 |
Clifford Wolf
|
e340532ce5
|
Added init= attribute for fpga-style reset values
|
2013-11-20 01:49:37 +01:00 |
Clifford Wolf
|
0dfdbd991a
|
Fixed parsing of module arguments when one type is used for many args
|
2013-11-19 20:35:31 +01:00 |
Clifford Wolf
|
4f2edcf2f9
|
Fixed two bugs in mem2reg functionality in AST frontend
|
2013-11-18 19:55:12 +01:00 |
Clifford Wolf
|
79910a5547
|
Added dumping of attributes in AST frontend
|
2013-11-18 19:54:36 +01:00 |
Clifford Wolf
|
2a25e3bca3
|
Fixed parsing of default cases when not last case
|
2013-11-18 16:10:50 +01:00 |
Clifford Wolf
|
de03184150
|
Fixed mem2reg for reg usage outside always block
|
2013-11-18 12:35:41 +01:00 |
Clifford Wolf
|
63060dcd2e
|
Fixed parsing of "parameter integer"
|
2013-11-13 15:30:23 +01:00 |
Clifford Wolf
|
e5b974fa2a
|
Cleanups and bugfixes in response to new internal cell checker
|
2013-11-11 00:39:45 +01:00 |
Clifford Wolf
|
378cc509cd
|
Call internal checker more often
|
2013-11-10 23:24:21 +01:00 |
Clifford Wolf
|
259cc1391e
|
More undef-propagation related fixes
|
2013-11-08 11:40:36 +01:00 |
Clifford Wolf
|
9f49d538e1
|
Fixed handling of different signedness in power operands
|
2013-11-08 11:06:11 +01:00 |
Clifford Wolf
|
4abc8e695a
|
Implemented const folding of ternary op with undef select
|
2013-11-08 04:44:09 +01:00 |
Clifford Wolf
|
fc6dc0d7b8
|
Fixed handling of power operator
|
2013-11-07 22:20:00 +01:00 |
Clifford Wolf
|
d7cb62ac96
|
Fixed more extend vs. extend_u0 issues
|
2013-11-07 19:20:20 +01:00 |
Clifford Wolf
|
02f4f89fdb
|
Disabled const folding of ternary op when select is undef
|
2013-11-07 18:18:16 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
ed4bcd52e5
|
Fixed sign handling in constants
|
2013-11-07 14:53:10 +01:00 |
Clifford Wolf
|
83a8b8b5ca
|
Fixed const folding in corner cases with parameters
|
2013-11-07 14:08:53 +01:00 |
Clifford Wolf
|
b52bf379b9
|
Fixed width detection for replicate operator
|
2013-11-07 12:43:04 +01:00 |
Clifford Wolf
|
536621a98b
|
Fixed at_zero evaluation of dynamic ranges
|
2013-11-07 11:25:19 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
160adccca2
|
Fixed the fix for propagation of width hints for $signed() and $unsigned()
|
2013-11-07 03:01:28 +01:00 |
Clifford Wolf
|
7fe13faefa
|
Fixed propagation of width hints for $signed() and $unsigned()
|
2013-11-06 22:41:21 +01:00 |
Clifford Wolf
|
baeca48a24
|
Additional fixes for undef propagation in concat and replicate ops
|
2013-11-06 21:16:54 +01:00 |
Clifford Wolf
|
6fcbc79b5c
|
Improved width extension with regard to undef propagation
|
2013-11-06 21:05:11 +01:00 |
Clifford Wolf
|
f2786df146
|
Another fix for early width and sign detection in ast simplifier
|
2013-11-04 21:29:36 +01:00 |
Clifford Wolf
|
d38c67f53d
|
Fixed const folding of ternary operator
|
2013-11-04 16:46:14 +01:00 |
Clifford Wolf
|
8d226da694
|
Use proper bit width ans sign extension for const folding
|
2013-11-04 15:37:09 +01:00 |
Clifford Wolf
|
1325514d33
|
Fixes for early width and sign detection in ast simplifier
|
2013-11-04 08:28:13 +01:00 |
Clifford Wolf
|
472117d532
|
further improved early width and sign detection in ast simplifier
|
2013-11-04 06:04:42 +01:00 |
Clifford Wolf
|
d2b083f5cb
|
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
|
2013-11-03 18:56:45 +01:00 |
Clifford Wolf
|
ada80545fa
|
Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
|
2013-11-02 21:13:01 +01:00 |
Clifford Wolf
|
943329c1dc
|
Various ast changes for early expression width detection (prep for constfold fixes)
|
2013-11-02 13:00:17 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Clifford Wolf
|
eae43e2db4
|
Fixed handling of boolean attributes (kernel)
|
2013-10-24 10:59:27 +02:00 |
Clifford Wolf
|
77726fb5fe
|
Fixed parsing of value-less attributes in ilang
|
2013-10-23 18:38:31 +02:00 |
Johann Glaser
|
f352205635
|
fixed Verilog parser filename and line numbering issue with include files
|
2013-08-21 09:20:59 +02:00 |
Johann Glaser
|
a99c224157
|
Added support for include directories with the new '-I' argument of the
'read_verilog' command
|
2013-08-20 15:48:16 +02:00 |
Johann Glaser
|
6c4cbc03c2
|
Added support for notif0/notif1 primitives
|
2013-08-20 11:23:59 +02:00 |
Clifford Wolf
|
0003743432
|
Fixed width and sign detection for ** operator
|
2013-08-19 20:58:01 +02:00 |
Clifford Wolf
|
8656b1c08f
|
Added support for bufif0/bufif1 primitives
|
2013-08-19 19:50:04 +02:00 |
Clifford Wolf
|
4214561890
|
Improved ast dumping (ast/verilog frontend)
|
2013-08-19 19:49:14 +02:00 |
Clifford Wolf
|
759852914d
|
Added support for "2**n" shifter encoding
|
2013-08-12 14:47:50 +02:00 |
Clifford Wolf
|
c8763301b4
|
Added $div and $mod technology mapping
|
2013-08-09 17:09:24 +02:00 |
Clifford Wolf
|
0f38008ed3
|
Added "design" command (-reset, -save, -load)
|
2013-07-27 14:27:51 +02:00 |
Clifford Wolf
|
3650fd7fbe
|
More fixes in ternary op sign handling
|
2013-07-12 13:13:04 +02:00 |
Clifford Wolf
|
ded769c98c
|
Fixed sign handling in ternary operator
|
2013-07-12 01:15:37 +02:00 |
Clifford Wolf
|
b380c8c790
|
Another vloghammer related bugfix
|
2013-07-11 19:24:59 +02:00 |
Clifford Wolf
|
ed62fcdbe2
|
Fixed sign propagation in bit-wise operators
|
2013-07-09 23:53:55 +02:00 |
Clifford Wolf
|
5dab327b30
|
More fixes in ast expression sign/width handling
|
2013-07-09 23:41:43 +02:00 |
Clifford Wolf
|
00a6c1d9a5
|
Major redesign of expr width/sign detecion (verilog/ast frontend)
|
2013-07-09 14:31:57 +02:00 |
Clifford Wolf
|
e8da3ea7b6
|
Fixed another bug found using vloghammer
|
2013-07-07 16:49:30 +02:00 |
Clifford Wolf
|
eff68560a2
|
Fixed AST_CONSTANT node generation
|
2013-07-07 15:40:26 +02:00 |
Clifford Wolf
|
56432a920f
|
Added defparam support to Verilog/AST frontend
|
2013-07-04 14:12:33 +02:00 |
Clifford Wolf
|
0c6ffc4c65
|
More fixes for bugs found using xsthammer
|
2013-06-13 11:18:45 +02:00 |
Clifford Wolf
|
4b311b7b99
|
Further improved and extended xsthammer
|
2013-06-11 19:49:35 +02:00 |
Clifford Wolf
|
a5c30183b5
|
Sign-extension related fixes in SatGen and AST frontend
|
2013-06-10 17:10:06 +02:00 |
Clifford Wolf
|
59dd02baa2
|
Fixes and improvements in AST const folding
|
2013-06-10 13:56:03 +02:00 |
Clifford Wolf
|
db98a18edb
|
Enabled AST/Verilog front-end optimizations per default
|
2013-06-10 13:19:04 +02:00 |
Clifford Wolf
|
46fbe9d262
|
Added SAT generator and simple sat_solve command
|
2013-06-07 13:59:13 +02:00 |
Clifford Wolf
|
ed0e2f7a6f
|
Added log_assert() api
|
2013-05-24 14:38:36 +02:00 |
Clifford Wolf
|
375f83c5ec
|
Fixed memory leak in ilang frontend
|
2013-05-23 12:55:59 +02:00 |
Johann Glaser
|
10a195c0a1
|
added option '-Dname[=definition]' to command 'read_verilog'
|
2013-05-19 17:07:52 +02:00 |
Clifford Wolf
|
c5ee2b306a
|
Merge branch 'bugfix'
|
2013-05-16 16:44:45 +02:00 |
Clifford Wolf
|
6cc8e848b6
|
Fixed synthesis of functions in latched blocks
|
2013-05-16 16:44:06 +02:00 |
Clifford Wolf
|
b56e06d2f5
|
Added support for verilog === operator
|
2013-05-07 14:35:40 +02:00 |
Clifford Wolf
|
8f2d90de4f
|
Fixed handling of positional module parameters
|
2013-04-26 14:40:25 +02:00 |
Clifford Wolf
|
453a29c9f6
|
Only use sha1 checksums for names of parametric modules when the verbose form is to long
|
2013-04-26 13:13:58 +02:00 |
Clifford Wolf
|
e0c408cb4a
|
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
|
2013-04-13 21:19:10 +02:00 |
Clifford Wolf
|
f1a2fd966f
|
Now only use value from "initial" when no matching "always" block is found
|
2013-03-31 11:51:12 +02:00 |
Clifford Wolf
|
161565be10
|
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
|
2013-03-31 11:19:11 +02:00 |
Clifford Wolf
|
7bfc7b61a8
|
Implemented proper handling of stub placeholder modules
|
2013-03-28 09:20:10 +01:00 |
Clifford Wolf
|
7a99349de4
|
Improvements and bugfixes for generate blocks with local signals
|
2013-03-26 11:31:34 +01:00 |
Clifford Wolf
|
6a382f2aba
|
Fixed handling of unconditional generate blocks
|
2013-03-26 09:44:54 +01:00 |
Clifford Wolf
|
227520f94d
|
Added nosync attribute and some async reset related fixes
|
2013-03-25 17:13:14 +01:00 |
Clifford Wolf
|
df9753d398
|
Added mem2reg option to verilog frontend
|
2013-03-24 11:13:32 +01:00 |
Clifford Wolf
|
3a5244e913
|
Another fix in mem2reg ast simplify logic
|
2013-03-24 10:42:08 +01:00 |
Clifford Wolf
|
bb3357c027
|
Improved mem2reg handling in ast simplifier
|
2013-03-24 09:27:01 +01:00 |
Clifford Wolf
|
e45d1c8865
|
Tiny fixes to verilog parser
|
2013-03-23 18:54:31 +01:00 |
Clifford Wolf
|
8a6b0a3520
|
Added help messages to ilang and verilog frontends
|
2013-03-01 08:03:00 +01:00 |
Clifford Wolf
|
a321a5c412
|
Moved stand-alone libs to libs/ directory and added libs/subcircuit
|
2013-02-27 09:32:19 +01:00 |
Clifford Wolf
|
4f0c2862a0
|
Added support for verilog genblock[index].member syntax
|
2013-02-26 13:18:22 +01:00 |
Clifford Wolf
|
6d1502b948
|
Added support for "always @(*)"
|
2013-01-16 17:32:11 +01:00 |
Clifford Wolf
|
6543917fb8
|
added .gitignore files
|
2013-01-05 11:19:11 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |