Eddie Hung
3a49aa6b4a
Tidy up
2019-09-11 14:20:49 -07:00
Eddie Hung
817ac7c5e0
Fix UB
2019-09-11 14:18:02 -07:00
Eddie Hung
63431fe42a
Fix UB
2019-09-11 14:17:45 -07:00
Eddie Hung
690b1a064d
Add PCOUT -> PCIN non-shifted cascading
2019-09-11 13:48:45 -07:00
Eddie Hung
c0f26c2da8
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 13:37:11 -07:00
Eddie Hung
bdb5e0f29c
Cope with presence of reset muxes too
2019-09-11 13:36:37 -07:00
Eddie Hung
4937917cd8
Cleanup
2019-09-11 13:22:52 -07:00
Eddie Hung
e9eb855d38
Make unextend a udata
2019-09-11 13:06:49 -07:00
Eddie Hung
bbef0d2ac8
Only display log message if did_something
2019-09-11 12:29:26 -07:00
Eddie Hung
d232e6a6cd
Input registers to add DSP as new siguser to block upstream packing
2019-09-11 11:46:21 -07:00
Eddie Hung
e5bdb521fa
More cleanup
2019-09-11 10:55:45 -07:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Eddie Hung
0d709d2bb5
Add support for A/B/C/D/AD reset
2019-09-11 10:15:19 -07:00
Eddie Hung
ded805ae5d
Add support for RSTM
2019-09-11 07:34:14 -07:00
David Shah
c43e52d2d7
Add equiv_opt -multiclock
...
Signed-off-by: David Shah <dave@ds0.me>
2019-09-11 13:55:59 +01:00
David Shah
c7f1368cd2
Merge pull request #1362 from xobs/smtbmc-msvc2-build-fixes
...
MSVC2 fixes
2019-09-11 09:57:30 +01:00
Eddie Hung
fc7008671f
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:57:25 -07:00
Eddie Hung
edf90afd20
Rename dffmuxext -> dffmux, also remove constants in dff+mux
2019-09-11 00:56:38 -07:00
Eddie Hung
6b23c7c227
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:07:33 -07:00
Eddie Hung
feb3fa65a3
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-11 00:01:31 -07:00
Eddie Hung
b08797da6b
Only pack out registers if \init is zero or x; then remove \init from PREG
2019-09-10 21:33:14 -07:00
Eddie Hung
37a34eeb04
Fix RSTP
2019-09-10 20:56:13 -07:00
Eddie Hung
af147d1430
Add support for RSTP
2019-09-10 20:51:48 -07:00
Eddie Hung
c6df55a9e7
enpol -> cepol
2019-09-10 18:59:03 -07:00
Eddie Hung
86700c2bea
d?ffmux -> d?ffcemux
2019-09-10 18:52:54 -07:00
Eddie Hung
8b8a68b38a
Refactor MREG and PREG to out_dffe subpattern
2019-09-10 18:27:05 -07:00
Eddie Hung
e64e650f9c
Update help text
2019-09-10 16:35:10 -07:00
Eddie Hung
d30b2a6d7e
Update xilinx_dsp help text
2019-09-10 16:33:13 -07:00
Eddie Hung
cba63fe72b
Oops
2019-09-09 22:06:23 -07:00
Eddie Hung
02cf9933b9
Support subtraction as well
2019-09-09 21:39:42 -07:00
Eddie Hung
31e60353ac
Support TWO24
2019-09-09 21:11:41 -07:00
Eddie Hung
0bb6fd8448
Refactor
2019-09-09 20:58:54 -07:00
Eddie Hung
5a6552e56b
Add initial USE_SIMD=FOUR12 support
2019-09-09 20:57:20 -07:00
Eddie Hung
2c04430445
Only trim sigM if USE_MULT; only look for ffM then too
2019-09-09 20:57:03 -07:00
Eddie Hung
be0eaf3a9a
Fix misspelling
2019-09-09 16:46:33 -07:00
Eddie Hung
6348f9512c
Rename
2019-09-09 16:45:38 -07:00
Eddie Hung
1df9c5d277
Oops
2019-09-09 16:07:40 -07:00
Eddie Hung
5f8f0e1383
Tidy up
2019-09-09 15:59:10 -07:00
Eddie Hung
04bc287271
Refactor using subpattern in_dffe
2019-09-09 15:51:14 -07:00
Sean Cross
8d128ba6d0
passes: opt_share: don't statically initialize mergeable_type_map
...
In 3d3779b037
this got turned from a
`std::map<std::string, std::string>` to `std::map<IdString, IdString>`.
Consequently, this exposed some initialization sequencing issues (#1361 ).
Only initialize the map when it's first used, to avoid these static issues.
This fixes #1361 .
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-09 12:40:01 +08:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Eddie Hung
e2c2d784c8
Make one check $shift(x)? only; change testcase to be 8b
2019-09-06 22:48:23 -07:00
Eddie Hung
74a5c802f7
Pack CREG
2019-09-06 21:01:36 -07:00
Eddie Hung
6a9205280f
Use unextend lambda
2019-09-06 18:40:11 -07:00
Eddie Hung
b69512a5b9
Fix ffP just like ffPmux
2019-09-06 15:51:21 -07:00
Eddie Hung
5344bfe637
Perform D replacement properly
2019-09-06 15:46:15 -07:00
Eddie Hung
74eac76699
Add support for DREG
2019-09-06 15:32:26 -07:00
Eddie Hung
ef56f8596f
Fine tune nusers when postAdd
2019-09-06 15:11:41 -07:00
Eddie Hung
0d1d8b4d24
Fix macc and mul tests
2019-09-06 14:57:36 -07:00
Eddie Hung
8246062acf
Fix enable polarity
2019-09-06 14:36:10 -07:00
Eddie Hung
2c32056990
Logging for ffAD
2019-09-06 14:10:12 -07:00
Eddie Hung
e926f2973e
Add support for pre-adder and AD register
2019-09-06 14:06:57 -07:00
Eddie Hung
ef77162ce4
Document (* gentb_skip *) attr for test_autotb
2019-09-06 13:28:15 -07:00
Eddie Hung
da8fe83f7a
Tidy up ice40_dsp some more
2019-09-06 12:16:40 -07:00
Eddie Hung
776d769941
Use more index patterns
2019-09-06 12:07:35 -07:00
Eddie Hung
a945f6c7ef
Fix ffPmux to cope with offset
2019-09-06 11:58:56 -07:00
Eddie Hung
fbf1b74946
Simplify filter expressions
2019-09-06 11:39:20 -07:00
Eddie Hung
39a5d046ea
Fix nusers condition in ffP
2019-09-06 11:38:19 -07:00
Eddie Hung
cdc1e1f5c2
Check adder is <= 48 bits before packing
2019-09-06 10:35:06 -07:00
Eddie Hung
91f68c4de2
Check nusers for M and P enable muxes
2019-09-06 09:59:35 -07:00
Eddie Hung
4fe24b20f9
More nusers() checks for A and B enable muxes
2019-09-06 09:47:32 -07:00
Eddie Hung
dc10559f31
Cleanup
2019-09-05 21:39:52 -07:00
Eddie Hung
174edbcb96
Sensitive to CEB CEM CEP polarity
2019-09-05 21:38:35 -07:00
Eddie Hung
53ca536d67
ffAmuxAB -> ffAenpol
2019-09-05 21:28:28 -07:00
Eddie Hung
5a2fc6fcb5
Refactor ice40_dsp
2019-09-05 18:06:59 -07:00
Eddie Hung
888ae1d05e
Fix broken ice40_dsp
2019-09-05 17:58:19 -07:00
Eddie Hung
38e73a3788
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-05 13:01:34 -07:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
Eddie Hung
a32b14a55f
Do not check signedness of post-adder (assume taken care of by DSP)
2019-09-05 12:38:47 -07:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
...
Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Eddie Hung
7bd55f379c
Use filter instead of index; support wide enable muxes
2019-09-05 11:55:14 -07:00
Eddie Hung
fe5a1324c9
Do not make ff[MP]mux semioptional, use sigmap
2019-09-05 11:46:38 -07:00
Eddie Hung
447a31e75d
Add support for CEP
2019-09-05 11:00:27 -07:00
Eddie Hung
05282afc25
Add support for CEB, remove check on nusers
2019-09-05 10:46:33 -07:00
Eddie Hung
0166e02e78
Cleanup
2019-09-05 10:07:56 -07:00
Eddie Hung
aa462da395
Support CEA
2019-09-05 10:07:26 -07:00
Clifford Wolf
30f1ac7ce9
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
Clifford Wolf
694a8f75cf
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:30:58 +02:00
Eddie Hung
09c26c55bb
Get rid of sigBset too
2019-09-04 17:22:02 -07:00
Eddie Hung
91ef4457b0
Get rid of sigAset
2019-09-04 17:18:49 -07:00
Eddie Hung
42548d9790
Get rid of sigPused
2019-09-04 17:06:17 -07:00
Eddie Hung
93d798272d
Compute sigP properly
2019-09-04 16:59:57 -07:00
Eddie Hung
ba629e6a28
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-04 15:36:07 -07:00
Eddie Hung
433b0c677c
Remove log_cell() calls
2019-09-04 13:42:44 -07:00
Eddie Hung
229e54568e
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-04 12:37:48 -07:00
Eddie Hung
3732d421c5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-04 12:37:42 -07:00
Eddie Hung
2b86055848
Add peepopt_dffmuxext
2019-09-04 12:35:15 -07:00
Eddie Hung
e67e4a5ed6
Support CEM
2019-09-04 10:52:51 -07:00
Eddie Hung
80aec0f006
st.ffP from if to assert
2019-09-03 16:37:59 -07:00
Eddie Hung
16316aa05d
Rename muxAB to postAddMux
2019-09-03 16:24:59 -07:00
Eddie Hung
cd002ad3fb
Use choices for addAB, now called postAdd
2019-09-03 16:10:16 -07:00
Eddie Hung
2d80866daf
Add support for load value into DSP48E1.P
2019-09-03 15:53:10 -07:00
Eddie Hung
682153de4b
Process post-adder first since C could be used for load-P
2019-09-03 14:57:59 -07:00
Eddie Hung
97d11708e0
Use feedback path for MACC
2019-09-03 14:37:32 -07:00
Eddie Hung
d2306d7b1d
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
Eddie Hung
d6a84a78a7
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
2019-09-03 10:49:21 -07:00
Eddie Hung
2fa3857963
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-02 12:13:44 -07:00
Eddie Hung
4aa505d1b2
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
...
ice40_dsp to allow signed multipliers
2019-09-01 10:11:33 -07:00
Miodrag Milanovic
fa5065e9b5
Fix select command error msg, fixes issue #1081
2019-09-01 11:00:09 +02:00
Eddie Hung
a09e69dd56
Fine tune xilinx_dsp pattern matcher
2019-08-30 16:18:58 -07:00
Eddie Hung
8f503fe3e6
autoremove ffM
2019-08-30 15:30:04 -07:00
Eddie Hung
e67f049e3b
Remove debug
2019-08-30 15:03:43 -07:00
Eddie Hung
15bab02a1b
ffM before addAB
2019-08-30 15:03:12 -07:00
Eddie Hung
c497114e94
Another oops
2019-08-30 15:02:53 -07:00
Eddie Hung
44a35015b3
Update commented out
2019-08-30 15:01:38 -07:00
Eddie Hung
390cf34d0a
Add support for ffM
2019-08-30 15:00:56 -07:00
Eddie Hung
2983a35dc0
Update comment
2019-08-30 15:00:40 -07:00
Eddie Hung
17b77fd411
Missing dep for test_pmgen
2019-08-30 14:01:07 -07:00
Eddie Hung
89359b6927
Missing dep for test_pmgen
2019-08-30 14:00:40 -07:00
Eddie Hung
723815b384
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
...
abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
c1459bc748
Do not restrict multiplier to unsigned
2019-08-30 12:22:14 -07:00
Eddie Hung
4e782f1509
New pmgen requires explicit accept
2019-08-30 11:02:10 -07:00
Eddie Hung
d2d2816f8c
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-30 10:30:54 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
295c18bd6b
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-30 09:50:20 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
Eddie Hung
116c249601
-auto-top should check $abstract (deferred) modules with (* top *)
2019-08-28 19:59:25 -07:00
Eddie Hung
4eb5847dbd
Cleanup
2019-08-28 18:10:33 -07:00
Eddie Hung
0af64df10c
Account for D port being a constant
2019-08-28 15:32:38 -07:00
Eddie Hung
a45c09c8d1
Account for D port being a constant
2019-08-28 15:31:55 -07:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch
...
Add $dlatch support to async2sync
2019-08-28 12:36:06 -07:00
Eddie Hung
52c4655de3
No need to replace Q of slice since $shiftx is autoremove-d
2019-08-28 11:06:11 -07:00
Eddie Hung
11e3eb1009
More cleanup
2019-08-28 10:19:35 -07:00
Eddie Hung
86b538bd02
More cleanup
2019-08-28 10:11:09 -07:00
Eddie Hung
c4d1bd988b
Do not use default_params dict, hardcode default values, cleanup
2019-08-28 10:06:40 -07:00
Eddie Hung
c3e9627afe
Always generate if no match
2019-08-28 09:54:56 -07:00
Eddie Hung
0ebe2c9831
Rename test_pmgen arg xilinx_srl.{fixed,variable}
2019-08-28 09:27:03 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Clifford Wolf
47ffbf554e
Fix typo
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c
Add "paramap" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73
Add $dlatch support to async2sync
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 09:45:22 +02:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init
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In sat: 'x' in init attr should be ignored
2019-08-28 00:18:14 +02:00
Eddie Hung
28133432be
Ignore all 1'bx in (* init *)
2019-08-27 09:24:59 -07:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
9172d4a674
Missing close bracket
2019-08-26 21:02:52 -07:00
Eddie Hung
6b5e65919a
Revert "In sat: 'x' in init attr should not override constant"
...
This reverts commit 2b37a093e9
.
2019-08-26 17:52:57 -07:00
Eddie Hung
54422c5bb4
Remove leftover header
2019-08-26 17:51:13 -07:00
Eddie Hung
e95fb24574
Improve xilinx_srl.fixed generate, add .variable generate
2019-08-26 17:49:08 -07:00
Eddie Hung
45c34c87ee
Account for maxsubcnt overflowing
2019-08-26 17:48:54 -07:00
Eddie Hung
b32d6bf403
Add xilinx_srl_pm.variable to test_pmgen
2019-08-26 17:44:57 -07:00
Eddie Hung
e574edc3e9
Populate generate for xilinx_srl.fixed pattern
2019-08-26 14:21:17 -07:00
Eddie Hung
cf9e017127
Add xilinx_srl_fixed, fix typos
2019-08-26 14:20:06 -07:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
7911143827
Create new $__XILINX_SHREG_ cell for variable length too
2019-08-23 18:15:49 -07:00
Eddie Hung
a048fc93e8
Do not allow Q of last cell of variable length SRL to be (* keep *)
2019-08-23 18:15:24 -07:00
Eddie Hung
ee9f6e6243
Also add first.Q to chain_bits since variable length
2019-08-23 18:14:06 -07:00
Eddie Hung
70ce3d0670
Do not enforce !EN_POLARITY on $dffe
2019-08-23 18:11:28 -07:00
Eddie Hung
188b49378a
Create new cell for fixed length SRL
2019-08-23 17:25:30 -07:00
Eddie Hung
e081303ee8
Cleanup FDRE matching
2019-08-23 17:23:52 -07:00
Eddie Hung
54488cfb82
Oops don't need a finally block
2019-08-23 16:39:37 -07:00
Eddie Hung
83e2d87fb8
Keep track of bits in variable length chain, to check for taps
2019-08-23 16:21:10 -07:00
Eddie Hung
f2d4814284
Don't forget $dff has no EN
2019-08-23 16:14:57 -07:00
Eddie Hung
2217d926a9
Same for variable length
2019-08-23 16:13:16 -07:00
Eddie Hung
b1caf7be5e
Filter on en_port for fixed length
2019-08-23 16:09:46 -07:00
Eddie Hung
513af10d77
Check clock is consistent
2019-08-23 15:18:26 -07:00
Eddie Hung
c762618783
Fix last_cell.D
2019-08-23 15:08:49 -07:00
Eddie Hung
ca5de78e76
Revert "Add a unique argument to pmgen's nusers()"
...
This reverts commit 1d88887cfd
.
2019-08-23 15:04:00 -07:00
Eddie Hung
e85e6e8d45
Revert "Fix polarity"
...
This reverts commit 9cd23cf0fe
.
2019-08-23 15:03:42 -07:00
Eddie Hung
9cd23cf0fe
Fix polarity
2019-08-23 14:49:34 -07:00
Eddie Hung
c2757613b6
Check for non unique nusers/fanouts
2019-08-23 14:32:36 -07:00
Eddie Hung
1d88887cfd
Add a unique argument to pmgen's nusers()
2019-08-23 14:32:17 -07:00
Eddie Hung
8ecfd55d5a
Update doc
2019-08-23 14:16:41 -07:00
Eddie Hung
3d7f4aa0c8
Remove (* init *) entry when consumed into SRL
2019-08-23 13:56:01 -07:00
Eddie Hung
48c424e45b
Cleanup
2019-08-23 13:46:05 -07:00
Eddie Hung
967a36c125
indo -> into
2019-08-23 13:16:50 -07:00
Eddie Hung
a1f78eab04
indo -> into
2019-08-23 13:15:41 -07:00
Eddie Hung
5939ffdc07
Forgot to slice
2019-08-23 13:06:59 -07:00
Eddie Hung
242b3083ea
Cope with possibility that D could connect to Q on same cell
2019-08-23 13:06:31 -07:00
Eddie Hung
18b64609c2
xilinx_srl to use 'slice' features of pmgen for word level
2019-08-23 12:22:06 -07:00
Eddie Hung
f4fd41d5d2
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
2019-08-23 11:35:06 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
619f2414e5
clkbufmap to only check clkbuf_inhibit if no selection given
2019-08-23 11:14:42 -07:00
Eddie Hung
4d89c3f468
Review comment from @cliffordwolf
2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Clifford Wolf
55bf8f69e0
Fix port hanlding in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:26:54 +02:00
Clifford Wolf
adb81ba386
Add pmgen slices and choices
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:15:50 +02:00
Eddie Hung
51ffb093b5
In sat: 'x' in init attr should not override constant
2019-08-22 16:43:08 -07:00
Eddie Hung
2b37a093e9
In sat: 'x' in init attr should not override constant
2019-08-22 16:42:19 -07:00
Eddie Hung
53fed4f7e9
Actually, there might not be any harm in updating sigmap...
2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5
Add comment as per @cliffordwolf
2019-08-22 16:16:56 -07:00
Eddie Hung
8691596d19
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
.
2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc
Try way that doesn't involve creating a new wire
2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde
If d_bit already in sigbit_chain_next, create extra wire
2019-08-22 16:16:34 -07:00
Eddie Hung
c50d68653d
Spelling
2019-08-22 16:06:36 -07:00
Eddie Hung
6e8fda8bf0
Add doc
2019-08-22 11:52:24 -07:00
Eddie Hung
cabadb85e2
Add copyright
2019-08-22 11:25:19 -07:00
Eddie Hung
36d94caec1
Remove `shregmap -tech xilinx` additions
2019-08-22 11:22:09 -07:00
Eddie Hung
9f3ed1726e
pmgen to also iterate over all module ports
2019-08-22 11:15:16 -07:00
Eddie Hung
74bd190d3b
Remove output_bits
2019-08-22 11:14:59 -07:00
Eddie Hung
231ddbf95c
Forgot to set ud_variable.minlen
2019-08-22 11:02:17 -07:00
Eddie Hung
61639d5387
Do not run xilinx_srl_pm in fixed loop
2019-08-22 10:51:04 -07:00
Eddie Hung
7188972645
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-22 10:32:54 -07:00
Eddie Hung
d0b2973413
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-22 10:32:06 -07:00
Eddie Hung
b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
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opt_expr to trim A port of $shiftx/$shift
2019-08-22 10:31:27 -07:00
Eddie Hung
9245f0d3f5
Copy-paste typo
2019-08-22 08:43:44 -07:00
Eddie Hung
6f971470f8
Respect opt_expr -keepdc as per @cliffordwolf
2019-08-22 08:37:27 -07:00
Eddie Hung
379f33af54
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
2019-08-22 08:22:23 -07:00
Eddie Hung
9e31f01b34
Add cover()
2019-08-22 08:06:24 -07:00
Eddie Hung
d0ffe7544c
Canonical form
2019-08-22 08:05:01 -07:00
Eddie Hung
d3a212ff91
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-21 21:53:55 -07:00
Eddie Hung
7d02d17b16
Reuse var
2019-08-21 19:18:40 -07:00
Eddie Hung
5c8344363f
Revert "Trim shiftx_width when upper bits are 1'bx"
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This reverts commit 7e7965ca7b
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2019-08-21 19:18:27 -07:00
Eddie Hung
c7859531c2
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-21 19:18:05 -07:00
Eddie Hung
7e7965ca7b
Trim shiftx_width when upper bits are 1'bx
2019-08-21 18:43:17 -07:00
Eddie Hung
ed7be3e6b6
Add comment
2019-08-21 17:36:38 -07:00
Eddie Hung
15188033da
Add variable length support to xilinx_srl
2019-08-21 17:34:40 -07:00
Eddie Hung
6d76ae4c65
Rename pattern to fixed
2019-08-21 15:46:58 -07:00
Eddie Hung
b0a3b430bf
attribute -> attr
2019-08-21 15:44:07 -07:00
Eddie Hung
61b4d7ae13
Use Cell::has_keep_attribute()
2019-08-21 15:41:46 -07:00
Eddie Hung
6fa9e03e4c
xilinx_srl to support FDRE and FDRE_1
2019-08-21 15:35:29 -07:00
Eddie Hung
3c8e8521a6
Fix polarity of EN_POL
2019-08-21 14:42:11 -07:00
Eddie Hung
a980f0d4be
Add CLKPOL == 0
2019-08-21 14:35:40 -07:00
Eddie Hung
1c7d721558
Reject if not minlen from inside pattern matcher
2019-08-21 14:26:24 -07:00
Eddie Hung
cab2bd083e
Get wire via SigBit
2019-08-21 13:47:47 -07:00
Eddie Hung
52fea5b658
Respect \keep on cells or wires
2019-08-21 13:42:03 -07:00
Eddie Hung
5ce0c31d0e
Add init support
2019-08-21 13:05:10 -07:00
Eddie Hung
df53fe12e7
Fix spacing
2019-08-21 12:54:11 -07:00
Eddie Hung
0250712486
Initial progress on xilinx_srl
2019-08-21 12:50:49 -07:00
Eddie Hung
8f69be9cc7
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-21 11:39:14 -07:00
Miodrag Milanovic
948b6f91a1
Fix test_pmgen deps
2019-08-21 17:00:24 +02:00
Clifford Wolf
7d8db1c053
Merge pull request #1314 from YosysHQ/eddie/fix_techmap
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techmap -max_iter to apply to each module individually
2019-08-21 09:12:56 +02:00
Eddie Hung
4cc74346f1
Fix compile error
2019-08-20 20:27:05 -07:00
Eddie Hung
9b9d759451
Fix copy-paste typo
2019-08-20 20:18:51 -07:00
Eddie Hung
b7a48e3e0f
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-20 20:18:17 -07:00
Eddie Hung
affe9c9c1a
Merge branch 'eddie/fix_techmap' into xaig_arrival
2019-08-20 20:06:47 -07:00
Eddie Hung
fe61dcce8b
Grammar
2019-08-20 20:05:51 -07:00
Eddie Hung
193eae0c84
techmap -max_iter to apply to each module individually
2019-08-20 19:50:20 -07:00
Eddie Hung
57493e328a
techmap -max_iter to apply to each module individually
2019-08-20 19:48:16 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
fad15d276d
retime_mode -> dff_mode
2019-08-20 18:08:58 -07:00
Eddie Hung
505d062daf
Fix use of {CLK,EN}_POLARITY, also add a FIXME
2019-08-20 13:33:31 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen
2019-08-20 11:39:23 +02:00
whitequark
749ff864aa
Merge pull request #1309 from whitequark/proc_clean-fix-1268
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proc_clean: fix order of switch insertion
2019-08-20 00:45:41 +00:00
Eddie Hung
1f03154a0c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 15:19:32 -07:00
Eddie Hung
e29df7d5fa
Remove debug
2019-08-19 12:44:43 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
7e010834eb
Fix typo
2019-08-19 10:41:18 -07:00