riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,182 Commits 72 Branches 8 Tags 104 MiB
Commit Graph

1349 Commits

Author SHA1 Message Date
tangxifan 335347a74f [Test] Bug fix 2021-10-30 15:48:25 -07:00
tangxifan 6277234125 [Flow] bug fix in BRAM-oriented yosys scripts 2021-10-30 15:34:30 -07:00
tangxifan be47e78289 [Arch] Change arch for Sapone test 2021-10-30 15:23:19 -07:00
tangxifan e6cc3c4942 [Flow] Enable flatten for dff-related yosys scripts 2021-10-30 15:12:34 -07:00
tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals 2021-10-30 15:11:07 -07:00
tangxifan 8dea7e80e6 [Flow] Update yosys script to not use sdff and dffe 2021-10-30 14:56:54 -07:00
tangxifan 40d11a45d9 [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade 2021-10-30 14:49:56 -07:00
tangxifan b7ad61227d [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:47:37 -07:00
tangxifan ec184ef532 [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:46:12 -07:00
tangxifan 0b770f3330 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:36:43 -07:00
tangxifan 59a622a910 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:34:37 -07:00
tangxifan 978c60e75b [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 13:29:38 -07:00
tangxifan 18bab18032 [Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release 2021-10-30 13:20:58 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan 94328351be [Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts 2021-10-30 12:00:06 -07:00
tangxifan 0a449cc24c [HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected 2021-10-30 11:45:01 -07:00
tangxifan 9c06041ce4 [Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff` 2021-10-30 11:27:40 -07:00
Aram Kostanyan a355977420 Adding Yosys+Verific support. 2021-10-29 18:34:27 +05:00
tangxifan b8d5920529 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-28 15:45:58 -07:00
Aram Kostanyan 2eef21a1af Fixed port names for mult_36x36 2021-10-26 19:14:43 +05:00
nadeemyaseen-rs 274252438a Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-20 20:13:46 +05:00
Christophe Alexandre c42acec81e Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py 2021-10-18 10:45:35 +00:00
Christophe Alexandre c3dd704bf3 Fixing typo in run_fpga_flow.py 2021-10-18 09:13:42 +00:00
Christophe Alexandre d411967159 Fixing small typo in run_fpga_flow.py 2021-10-15 10:01:12 +00:00
nadeemyaseen-rs e0cfd46ec7 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-14 19:25:31 +05:00
tangxifan b2c4e3314e [Test] Bug fix in test cases 2021-10-11 10:28:09 -07:00
tangxifan 8566e2a0cd [Test] Renaming test case to follow naming convention as other fabric key test cases 2021-10-11 09:56:23 -07:00
tangxifan 2bf203cd00 [Test] Deploy the new test to basic regression test 2021-10-11 09:54:39 -07:00
tangxifan b8b02d37d5 [Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file 2021-10-11 09:53:23 -07:00
tangxifan cdcb07256b [Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization 2021-10-11 09:49:22 -07:00
tangxifan 982a324e0d [Test] Temporarily disable some tests; Will go back later 2021-10-10 23:30:50 -07:00
tangxifan 40fd89fdb4 [arch] Update fabric key for multi-region 2021-10-10 22:03:49 -07:00
tangxifan 8f9e564cd5 [Test] Add the new test to basic regression test 2021-10-09 20:45:23 -07:00
tangxifan 6122863548 [Test] Add a test case to validate the multi-shift-register-chain QL memory bank 2021-10-09 20:44:28 -07:00
tangxifan 82e77b42c5 [Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA 2021-10-09 20:43:55 -07:00
tangxifan 8aa2647878 [Script] Bug fix in slow clock frequency in shift register chain contraints 2021-10-06 16:49:01 -07:00
tangxifan dc5aedc393 [Script] Correct naming for clocks in shifter register chain defined in simulation setting files 2021-10-06 13:36:35 -07:00
tangxifan a1eaacf5a8 [Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency 2021-10-06 12:12:15 -07:00
tangxifan 554018449e [Test] Update regression test script 2021-10-06 12:10:37 -07:00
tangxifan b98a8ec718 [Test] Added the dedicated test case for fixed shift register clock frequency 2021-10-06 12:09:26 -07:00
tangxifan 169bb5fa45 [Script] Add an example simulation setting file with a fixed clock frequency for shift registers 2021-10-06 11:58:50 -07:00
tangxifan 189ade6c1e [Test] Bug fix 2021-10-05 19:17:34 -07:00
tangxifan f74ea5d39a [Test] Use the new openfpga shell script in don't care bit tests 2021-10-05 19:14:44 -07:00
tangxifan 4add9781d5 [Script] Add a new openfpga shell script for don't care bits outputting 2021-10-05 19:13:50 -07:00
tangxifan 50604e4589 [Test] move test cases 2021-10-05 19:02:43 -07:00
tangxifan 064ac478f3 [Test] Deploy news test to fpga-bitstream regression tests 2021-10-05 19:01:03 -07:00
tangxifan fed6c133b1 [Test] Add new tests to validate the correctness of bitstream files with don't care bits 2021-10-05 18:59:33 -07:00
tangxifan 80fd1efd61 [Test] Add an example test key for multi-region QuickLogic memory bank using shift registers 2021-10-05 11:46:58 -07:00
tangxifan b21f212031 [Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key 2021-10-05 11:39:53 -07:00
tangxifan 492db50efe [Test] Deploy the new test to basic regression tests 2021-10-05 10:59:26 -07:00
tangxifan 52569f808e [Test] Added a test case for QuickLogic memory bank using shift registers in multiple region 2021-10-05 10:57:33 -07:00
tangxifan d2859ca1c8 [Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers 2021-10-05 10:56:20 -07:00
tangxifan fbef22b494 [Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers 2021-10-04 16:39:53 -07:00
tangxifan 13c31cb89c [Test] Deploy the qlbanksr_wlr to basic regression tests 2021-10-04 16:37:49 -07:00
tangxifan fa1908511d [Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control 2021-10-04 16:36:20 -07:00
tangxifan 7f75c2b619 [Test] Deploy shift register -based QL memory bank test case to basic regression test 2021-10-03 16:06:44 -07:00
tangxifan 86e7c963f8 [Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files 2021-10-02 22:19:20 -07:00
tangxifan 0b06820177 [HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals 2021-10-01 17:06:35 -07:00
tangxifan 7ba5d27ea7 [Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model 2021-10-01 17:02:35 -07:00
tangxifan ff6f7e80f6 [Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers 2021-10-01 16:52:06 -07:00
tangxifan dda147e234 [Flow] Add an example simulation setting file for defining programming shift register clocks 2021-10-01 11:04:23 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan fa57117f50 [Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers 2021-10-01 10:19:51 -07:00
tangxifan 41cc375746 [Arch] define default CCFF model in ql bank example architecture that uses shift registers 2021-09-29 16:34:40 -07:00
tangxifan 89a97d83bd [Test] Added a new test case for the shift register banks in QuickLogic memory banks 2021-09-29 16:28:06 -07:00
tangxifan 4968f0d11f Merge branch 'master' into qlbank_sr 2021-09-28 14:20:30 -07:00
tangxifan 80232fc459 [Arch] Add a new example architecture for QL memory bank using WLR in shift registers 2021-09-28 12:36:36 -07:00
tangxifan 4c04c0fbd7 [Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models 2021-09-28 12:35:42 -07:00
tangxifan 2ce2fb269a [HDL] Added a different FF model which is designed to drive WLW only 2021-09-28 12:35:13 -07:00
tangxifan 6469ee3048 [HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs 2021-09-28 12:21:54 -07:00
tangxifan 4400dae108 [Test] Bug fix in the wrong arch name 2021-09-28 11:40:25 -07:00
tangxifan 4aed045cdd [Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs 2021-09-28 11:34:20 -07:00
tangxifan 811c898173 [Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests 2021-09-28 11:29:45 -07:00
tangxifan dae3554fd4 [Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals 2021-09-28 11:27:49 -07:00
tangxifan 1ca1b0f3e9 [Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests 2021-09-22 15:58:05 -07:00
tangxifan 655b195d8b [Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level 2021-09-22 15:56:44 -07:00
tangxifan a98df811ed [Arch] Bug fix: wrong circuit model name was used for CCFF 2021-09-22 15:50:47 -07:00
tangxifan 53da5d49fe [Arch] Correct XML syntax errors 2021-09-22 15:48:14 -07:00
tangxifan 3cfd5c3531 [Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks 2021-09-22 15:04:59 -07:00
tangxifan 212c5bd642 [Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization 2021-09-22 15:04:19 -07:00
tangxifan b0aaab9c03 [Test] Bug fix due to mismatches in device layout between fabric key and VPR settings 2021-09-22 11:32:13 -07:00
tangxifan efed268585 [Test] Deploy new test (for multi-region QL memory bank) to basic regression tests 2021-09-22 11:30:08 -07:00
tangxifan abfa380333 [Test] Added a test case to validate the fabric key of 2-region QL memory bank 2021-09-22 11:27:09 -07:00
tangxifan 337ed33b68 [Test] Added a sample fabric key for 2-region QL memory bank 2021-09-22 11:25:16 -07:00
tangxifan 7db7e2d8f6 [Test] Deploy the new test case for multi region QL memory bank to basic regression tests 2021-09-22 10:05:27 -07:00
tangxifan d0fe12fadd [Arch] Add an example OpenFPGA architecture for 2-region QL memory bank 2021-09-22 10:03:39 -07:00
tangxifan 51fc222d61 [Test] Added a new test case for multi-region QL memory bank 2021-09-22 10:01:33 -07:00
tangxifan ab42239b94 [Test] Bug fix in the fabric key 2021-09-21 16:44:58 -07:00
tangxifan f57aceff87 [Test] Deploy the load external key test case for ql memory bank to basic regression tests 2021-09-21 16:25:14 -07:00
tangxifan aad47ffbc6 [Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric 2021-09-21 16:22:50 -07:00
tangxifan 1412121541 [Test] Added a new test to validate the fabric key parser for QL memory bank 2021-09-21 16:20:24 -07:00
tangxifan cd0d8b86fa [Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank 2021-09-21 15:55:34 -07:00
tangxifan 7327850cf3 [Test] Deploy the fabric key test case for ql memory bank to basic regression tests 2021-09-21 15:43:54 -07:00
tangxifan dc2d1d1c3c [Test] Add a new test case to validate the correctness of fabric key file for ql memory bank 2021-09-21 15:42:20 -07:00
tangxifan d36d1ebee2 [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tangxifan 0450d57d82 [Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR 2021-09-20 16:05:01 -07:00
tangxifan 3f6ac41868 [Test] Deploy the WLR test to the basic regression tests 2021-09-20 11:21:58 -07:00
tangxifan 60fc3ab36c [Test] Added a new test case for the WLR memory bank 2021-09-20 11:20:36 -07:00
tangxifan 5c1c428ea5 [HDL] Updated cell library with the SRAM cell with Read Enable signal 2021-09-20 11:13:36 -07:00
tangxifan cd2978a434 [Arch] Added a new architecture example which shows how to use the memory bank with readback functionality 2021-09-20 11:13:02 -07:00
slt b867db815f
Update fpgaflow_default_tool_path.conf 
Update regex for VPR
 2021-09-17 14:02:26 +08:00
tangxifan 81a2ad58df [Test] Deploy the ql memory bank test case to basic regression tests (run on CI) 2021-09-09 13:48:30 -07:00
tangxifan b82cfdf555 [Test] Add the QL memory bank test to regression test cases 2021-09-09 09:29:21 -07:00
tangxifan 6be3c64f1c [Arch] Add an example architecture using the physical design friendly memory bank organization 2021-09-09 09:22:27 -07:00
tangxifan 6adf439081 Merge remote-tracking branch 'upstream/master' 2021-09-01 14:19:00 -07:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 006b54c4bc ready for merge 2021-07-01 15:35:39 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
komaljaved-rs be14e4f448 added design_variables.yml 2021-07-01 16:31:42 +05:00
komaljaved-rs 6559f71082 added ci_scripts 2021-07-01 15:07:37 +05:00
Andrew Pond fab2b069f0 added signal gen regression test to shell script 2021-06-30 16:18:09 -06:00
tangxifan a898537474 [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` 2021-06-30 15:29:13 -06:00
tangxifan 83d177b13b [Test] Deploy the newly added adder benchmarks to tests 2021-06-30 15:14:24 -06:00
tangxifan 4d4577bb83 [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders 2021-06-30 15:13:47 -06:00
tangxifan 9eeec05a1f [Test] Bug fix 2021-06-29 19:55:07 -06:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00
tangxifan 5f5a03f17f [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches 2021-06-29 18:28:38 -06:00
tangxifan 2c1692e6dc [Test] Bug fix 2021-06-29 17:54:25 -06:00
tangxifan 4fb34642ca [Script] Add a new example script for global tile clock running full testbench 2021-06-29 17:53:56 -06:00
tangxifan 9655bc35cb [Script] Bug fix due to the full testbench generation changes 2021-06-29 17:04:19 -06:00
tangxifan cbea4a3cb6 [Test] Add the test cases to regression test 2021-06-29 16:08:22 -06:00
tangxifan 30c2f597f2 [Test] Added two cases to validate testbench generation without self checking 2021-06-29 16:06:15 -06:00
tangxifan 20faf82e64 [Script] Rename example script 2021-06-29 16:02:35 -06:00
tangxifan 01391fd81e [Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features 2021-06-29 15:56:33 -06:00
tangxifan 7119075253 [Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated 2021-06-29 15:52:42 -06:00
tangxifan 75a12e55de [HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes 2021-06-29 11:40:22 -06:00
tangxifan b4c587f10b [Test] Added the new test cases to regression tests 2021-06-27 19:58:15 -06:00
tangxifan 6f0600e17f [Test] Added two test cases for generating preconfigured fabric wrapper in different styles 2021-06-27 19:56:01 -06:00
tangxifan 4a623bec79 [Script] Add example openfpga shell script to generate preconfigured fabric wrapper 2021-06-27 19:55:40 -06:00
tangxifan fae5e1dfdf [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' 2021-06-25 15:16:37 -06:00
tangxifan 477cba1c7e
Merge branch 'master' into verilog_testbench 2021-06-23 09:18:18 -06:00
tangxifan b2c30e3103 [Test] Bug fix in mcnc openfpga shell script 2021-06-22 16:40:24 -06:00
tangxifan e34fbf8ecf [Test] Deploy MCNC big20 to the micro benchmark regression test 2021-06-22 16:36:04 -06:00
tangxifan f06017581c [Test] Bug fix in counter micro benchmark tests 2021-06-22 16:33:50 -06:00
tangxifan 0a0d10b36d [HDL] Bug fix in Verilog syntax 2021-06-22 16:18:46 -06:00
tangxifan 4421dfcbbd
Merge branch 'master' into micro_benchmark 2021-06-22 14:29:29 -06:00
tangxifan fd580bb36f [Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name 2021-06-22 11:45:23 -06:00
tangxifan 0b2d6eb147 [Test] Add micro benchmark to a dedicated regression test 2021-06-21 18:35:41 -06:00
tangxifan 760570d883 [Test] Update counter test case for cover most counter HDL design 2021-06-21 18:13:18 -06:00
tangxifan 9c24a739be [Test] Added a MAC benchmark sweeping test 2021-06-21 17:40:53 -06:00
tangxifan 07dcf3ad27 [HDL] Add more micro benchmarks for counter, and-gate and mac unit 2021-06-21 16:48:35 -06:00
tangxifan f9e66e1bae [Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name; 2021-06-21 15:27:12 -06:00
tangxifan fce84e564d [Script] Patch on missing string to show in error message 2021-06-18 11:20:35 -06:00
tangxifan 0e01177cf0 [Script] Now openfpga flow script output detailed error message when task is not found 2021-06-18 11:01:45 -06:00
tangxifan 96cb3081ab
Update fix_device_route_chan_width_example_script.openfpga 2021-06-18 09:51:16 -06:00
Andrew Pond 3cfc42cdf9 added testbench CI 2021-06-15 14:16:31 -06:00
tangxifan d40cf98c48 [Test] Update test cases by using default net type in testbench generator 2021-06-14 11:47:28 -06:00
tangxifan eed30605d7 [Test] patch test case 2021-06-09 15:20:55 -06:00
tangxifan d545069aac [Script] Bug fix 2021-06-09 14:50:37 -06:00
tangxifan 52c0ed571b [Test] Patch test case to use proper template 2021-06-09 14:27:02 -06:00
tangxifan c62666e7c3 [Test] Use proper template for some failing tests 2021-06-09 14:24:34 -06:00
tangxifan 4e3f589810 [Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench' 2021-06-09 13:53:28 -06:00
tangxifan f9404dc97d [Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench' 2021-06-09 11:55:25 -06:00
tangxifan 9adf94bfd3 [Script] Update all the openshell scripts to deprecate 'write_verilog_testbench' 2021-06-09 11:18:52 -06:00
tangxifan be26c06673 [Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench' 2021-06-09 10:41:22 -06:00
tangxifan 462326aaa5 [Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench' 2021-06-07 21:50:00 -06:00
tangxifan 5ecd975ec7 [Test] Bug fix 2021-06-07 19:20:10 -06:00
tangxifan 9556f994b4 [Test] Use 'write_full_testbench' in all the memory bank -related test cases 2021-06-07 17:49:40 -06:00
tangxifan a67196178e [Test] Now use 'write_full_testbench' in configuration frame test cases 2021-06-07 13:58:15 -06:00
tangxifan 27fa15603a [Tool] Patch test case due to changes in the template script 2021-06-04 18:17:47 -06:00
tangxifan e9fa44cc25 [Tool] Add fast configuration to the write bitstream command in example shell script 2021-06-04 16:24:56 -06:00
tangxifan 5f96d440ec [Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration 2021-06-04 11:48:05 -06:00
tangxifan ec203d3a5c [Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases 2021-06-04 11:35:23 -06:00
tangxifan 2068291de0 [Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases 2021-06-04 11:32:49 -06:00
tangxifan aa4e1f5f9a [Test] Update test case which uses write_full_testbench openfpga shell script 2021-06-04 11:29:43 -06:00
tangxifan f5e90c9467 [Script] Update openfpga shell script with fast configuration option 2021-06-04 11:28:10 -06:00
tangxifan ebe30fc070 [Test] Deploy write full testbench to multi-head configuration chain test case 2021-06-03 17:08:33 -06:00
tangxifan 8fc90637e0 [Script] Update write_full_testbench example script to support custom device layout in VPR 2021-06-03 17:08:08 -06:00
tangxifan 1e9f6eb439 [Test] update configuration chain test to use new testbench 2021-06-03 15:53:27 -06:00
tangxifan 51ca62a464 [Script] Add example script for write_full_testbench command 2021-06-03 15:48:59 -06:00
Andrew Pond 12b44e0eca added configuration benchmark files 2021-05-13 10:04:23 -06:00
tangxifan c33ca464dc [Test] Deploy new tests to regression test 2021-05-07 12:06:46 -06:00
tangxifan 2baf3ddd2f [Test] Add test cases for 'report_bitstream_distribution' command 2021-05-07 12:06:24 -06:00
tangxifan 7dc7c1b4f5 [Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command 2021-05-07 12:05:47 -06:00
tangxifan f1658cb735 [Test] Deploy blinking to test cases 2021-05-06 15:17:45 -06:00
tangxifan 16fff90607 [Benchmark] Add microbenchmark 1-bit blinking 2021-05-06 15:17:27 -06:00
tangxifan f77b81fe5b [Arch] recover the mem16k arch as it is used in other test cases 2021-04-28 15:05:30 -06:00
tangxifan bc34efe337 [Arch] Bug fix in the architecture using BRAM spanning two columns 2021-04-28 14:32:17 -06:00
tangxifan a5e40fbb21
Merge branch 'master' into micro_benchmarks 2021-04-28 14:27:58 -06:00
tangxifan 870432e7f1 [Test] Patch regression test script due to the change of DPRAM test case 2021-04-28 12:45:52 -06:00
tangxifan b72d4bd807 [Test] Update test case for 1kbit DPRAM architectures 2021-04-28 11:28:53 -06:00
tangxifan 117cea295d [Arch] Patch architecture to be compatible with pin names of DPRAM cell 2021-04-28 11:28:23 -06:00
tangxifan a571b063b6 [Benchmark] Add 1k DPRAM benchmark which can fit new arch 2021-04-28 11:26:31 -06:00
tangxifan c24edbd674 [Script] Update yosys script due to arch changes in DPRAM sizes 2021-04-28 10:55:59 -06:00
tangxifan ec4b60f3cc [Arch] Add example arch using 1-kbit DPRAM 2021-04-28 10:47:17 -06:00
tangxifan be98775ae5 [Arch] Reduce the size of DPRAM in example architecture to accelerate testing 2021-04-28 10:45:10 -06:00
tangxifan 5c729657ef [Test] Bug fix in test case for DPRAM whose width = 2 2021-04-28 10:31:22 -06:00
tangxifan 79b27a6329 [Arch] Patch arch using DPRAM block with wide = 2 2021-04-28 10:29:09 -06:00
tangxifan 63309ba72b [HDL] Patch dpram cell 2021-04-27 23:42:31 -06:00
tangxifan 411af10933 [Script] Patch yosys script for 16kbit dual port RAM 2021-04-27 23:41:47 -06:00
tangxifan 834657f2da [Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes 2021-04-27 23:41:14 -06:00
tangxifan 0bec4b3f32 [Test] Update task configuration to use proper openfpgashell script 2021-04-27 23:34:42 -06:00
tangxifan 7d059f7407 [Benchmark] Bug fix in dual port ram 16k benchmark 2021-04-27 23:33:20 -06:00
tangxifan 3c1c33bf1e [Benchmark] Add a microbenchmark just fit 16k dual port ram 2021-04-27 22:51:43 -06:00
tangxifan 7e2368158e [Benchmark] move benchmarks to microbenchmark category 2021-04-27 22:12:30 -06:00
tangxifan 5a85ec9fa0 [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
tangxifan dd46780865 [Script] Update yosys script using BRAMs 2021-04-27 21:44:27 -06:00
tangxifan fdfbdc4613 [Test] Update task configuration files to use dedicated yosys script 2021-04-27 20:05:04 -06:00
tangxifan 2802b0895c [HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM 2021-04-27 19:55:46 -06:00
tangxifan e67095edd2 [HDL] Add 16k-bit dual port ram verilog 2021-04-27 19:55:16 -06:00
tangxifan 0f8aaae2bc [Arch] Patch architecture using 16kbit dual port RAM 2021-04-27 19:54:34 -06:00
tangxifan 1d498bb296 [Benchmark] Add a scalable micro benchmark fifo 2021-04-27 15:26:52 -06:00
tangxifan 6cb4d7d720 [Test] Add the new test to regressiont test 2021-04-27 14:41:38 -06:00
tangxifan b8ced5377f [Test] Add a test case for i/o mapping writer 2021-04-27 14:41:15 -06:00
tangxifan f9fd444b86 [Script] Add an write I/O mapping example script for openfpga shell 2021-04-27 14:40:26 -06:00
tangxifan 1d5e926d9e [Test] Deploy new test to CI 2021-04-26 16:29:54 -06:00
tangxifan 6291871faf [Test] Added a test for the example architecture with 2x2 DSP blocks 2021-04-26 16:28:43 -06:00
tangxifan 8c007c7c49 [Arch] Add a new example architecture where a DSP block occupies a 2x2 grid 2021-04-26 16:28:10 -06:00
tangxifan 7d4c5e3cd1 [Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block 2021-04-26 12:00:57 -06:00
tangxifan 6e87b8875b [Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block 2021-04-26 11:59:25 -06:00
tangxifan b7da22501c [Test] Deply new test to regression test 2021-04-24 15:55:05 -06:00
tangxifan 5adffad602 [Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!! 2021-04-24 15:49:53 -06:00
tangxifan 80f98328df [Test] Update test settings for architecture with fracturable DSP blocks 2021-04-24 15:16:50 -06:00
tangxifan 8b8096f3a8 [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition 2021-04-24 14:56:10 -06:00
tangxifan 4f454abfde [Arch] Add a new architecture using fracturable 16-bit DSP blocks 2021-04-24 14:01:42 -06:00
tangxifan 272d1fffb7 [HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks 2021-04-24 13:30:46 -06:00
tangxifan ddcdb35b28 [Arch] Bug fix in single-mode 8-bit DSP architectures 2021-04-24 13:30:03 -06:00
tangxifan 1c6b9a23d7 [Test] Add new test for multi-mode 16-bit DSP blocks 2021-04-24 13:29:29 -06:00
tangxifan c44688739d [HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks 2021-04-23 22:12:26 -06:00
tangxifan 09cc7f0007 [Script] Enable constant net routing for heterogeneous FPGAs 2021-04-23 20:44:36 -06:00
tangxifan 189c94ff19 [Test] Deploy new mac benchmarks to tests 2021-04-23 20:44:14 -06:00
tangxifan 200b6d39a6 [Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit 2021-04-23 20:36:28 -06:00
tangxifan 671394ec2c [Benchmark] Add microbenchmarks for mac with different sizes for DSP testing 2021-04-23 20:33:43 -06:00
tangxifan cbb7d41b6e [Script] Enable constant net routing for VTR benchmarks 2021-04-23 14:15:13 -06:00
tangxifan 784713e88a [Test] Add golden results for IWLS2005 as a simple QoR check 2021-04-22 19:27:31 -06:00