tangxifan
|
6c73e75bae
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[test] help to check diff. in golden netlists
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2022-09-17 10:42:49 -07:00 |
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tangxifan
|
a8d7b6c2c4
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[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
|
a2e22787c2
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[test] deploy the new test cases to the basic regression tests
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2022-09-16 10:31:15 -07:00 |
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tangxifan
|
10e86d334a
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[test] add test cases to validate the various layouts where I/Os are in the center of the grid
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2022-09-16 10:29:19 -07:00 |
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tangxifan
|
f2e13e5ea9
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[arch] add more flexible layout to test I/O center features
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2022-09-16 10:00:08 -07:00 |
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tangxifan
|
ec38b3990f
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[arch] update to check OpenFPGA I/O indexing
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2022-09-14 13:58:12 -07:00 |
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tangxifan
|
83c89ae1bf
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[arch] add more corner case to test the custom I/O location feature
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2022-09-13 23:05:41 -07:00 |
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tangxifan
|
330785635d
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[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
|
a37e270f25
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[arch] now custom I/O loc test case cover I/Os in the center of the fabric
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2022-09-13 16:57:18 -07:00 |
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tangxifan
|
1c2192a87d
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[engine] fixed a few bugs
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2022-09-12 16:50:32 -07:00 |
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tangxifan
|
0d6e4e3979
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[test] add a new example for the repack options
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2022-09-12 16:21:49 -07:00 |
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tangxifan
|
a3d070ac6f
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[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
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2022-09-12 10:43:21 -07:00 |
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tangxifan
|
314f5395b4
|
[benchmark] fixed a bug which causes yosys failed
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2022-09-09 17:04:59 -07:00 |
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tangxifan
|
91fe27ff66
|
[test] deploy new test to ci
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2022-09-09 17:00:28 -07:00 |
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tangxifan
|
1ab7590603
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[test] added a new test case to
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2022-09-09 16:59:06 -07:00 |
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tangxifan
|
cc974a80f7
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[arch] added a new architecture to test the local routing architecture where reset is on LUT
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2022-09-09 16:48:10 -07:00 |
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tangxifan
|
7a38c7dd18
|
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
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2022-09-09 16:42:55 -07:00 |
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tangxifan
|
d4523e819c
|
[test] fixed a bug
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2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
419a3a1e46
|
[arch] fixed a bug
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2022-09-08 16:53:52 -07:00 |
|
tangxifan
|
122a323668
|
[arch] fixed bugs
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2022-09-08 16:50:33 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
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2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
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2022-09-08 16:31:52 -07:00 |
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tangxifan
|
a840aeea7a
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[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
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2022-09-08 16:27:11 -07:00 |
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tangxifan
|
b1fad0b4e5
|
[arch] add an example architecture to show the use extended syntax
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2022-09-08 16:19:21 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
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2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
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2022-09-06 14:59:00 -07:00 |
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tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
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2022-09-06 14:04:23 -07:00 |
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tangxifan
|
c48f750f86
|
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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2022-09-01 20:10:29 -07:00 |
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tangxifan
|
51dc082bd4
|
[test] force a fixed routing chan W for no time stamp test case
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2022-09-01 15:02:40 -07:00 |
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tangxifan
|
d86eb04c5d
|
[test] now no timestamp test case covers gsb files
|
2022-09-01 14:03:51 -07:00 |
|
tangxifan
|
201bca8968
|
[test] typo
|
2022-08-30 08:59:20 -07:00 |
|
tangxifan
|
5f88b9a226
|
[test] typo
|
2022-08-29 22:41:15 -07:00 |
|
tangxifan
|
0b5bdcdbb1
|
[test] deploy new test to basic regression tests
|
2022-08-29 22:07:56 -07:00 |
|
tangxifan
|
069e2b00b1
|
[test] add more test cases to validate gsb options
|
2022-08-29 22:03:06 -07:00 |
|
tangxifan
|
6ce1d4804c
|
[test] deploy new test case to basic regression tests
|
2022-08-01 21:05:05 -07:00 |
|
tangxifan
|
9ea4a7c90f
|
[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
|
tangxifan
|
8b17bf1b1c
|
[test] add a new test case to validate that .act file is not required when power analysis flow is off
|
2022-08-01 18:44:47 -07:00 |
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tangxifan
|
55c7b75ab6
|
[script] even when power analysis mode is turned off, if users define a act file, still use it
|
2022-08-01 18:13:57 -07:00 |
root
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0da44ad1fc
|
[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
|
2022-08-02 08:02:28 +08:00 |
|
tangxifan
|
35fe858035
|
[test] fixed a few bugs
|
2022-07-28 12:06:16 -07:00 |
|
tangxifan
|
ca9122ddb9
|
[test] fixed a bug
|
2022-07-28 11:57:47 -07:00 |
|
tangxifan
|
ec31e124b7
|
[test] reworked test case on pcf2place
|
2022-07-28 11:51:56 -07:00 |
|
tangxifan
|
23f98d6a3b
|
[engine] fixed a few bugs
|
2022-07-26 13:55:29 -07:00 |
|
tangxifan
|
353de4546f
|
[test] add 'write_fabric_io_info' command to test cases
|
2022-07-26 13:48:54 -07:00 |
taoli4rs
|
347a29f27c
|
Fix test name in basic regression test script.
|
2022-07-20 21:05:31 -07:00 |
|
taoli4rs
|
3762a3aae4
|
Code clean up based on review.
|
2022-07-20 14:34:44 -07:00 |
|
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
4b9431b132
|
[test] avoid XML bitstream output when can go beyond github runners' disk space
|
2022-05-25 18:45:26 +08:00 |
|
tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
|
tangxifan
|
86347a9d49
|
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |