Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
84f3a796e1
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b
Un-break default specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
fb7f02be55
New behavior for front-end handling of whiteboxes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 22:24:50 +02:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Clifford Wolf
584d2030bf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-29 16:32:44 +01:00
Clifford Wolf
9b0e7af6d7
Improve read_verilog debug output capabilities
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 20:52:29 +01:00
Clifford Wolf
b02d9c2634
Fix handling of cases that look like sva labels, fixes #862
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-10 16:27:18 -07:00
Clifford Wolf
e7a34d342e
Also add support for labels on sva module items, fixes #699
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 22:55:09 -08:00
Clifford Wolf
22ff60850e
Add support for SVA labels in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:17:32 -08:00
Clifford Wolf
17ceab92a9
Bugfix in Verilog string handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-05 12:10:24 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Sylvain Munaut
58fb2ac818
verilog_parser: Properly handle recursion when processing attributes
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Fixes #737
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
Clifford Wolf
36ea98385f
Add warning for SV "restrict" without "property"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 15:57:17 +01:00
Clifford Wolf
5ab58d4930
Fix minor typo in error message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-25 13:20:00 +02:00
Udi Finkelstein
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
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meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
argama
097da32e1a
ignore protect endprotect
2018-10-16 21:33:37 +08:00
Ruben Undheim
736105b046
Handle FIXME for modport members without type directly in front
2018-10-13 20:50:33 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Clifford Wolf
8fde05dfa5
Add "read_verilog -noassert -noassume -assert-assumes"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-24 20:51:16 +02:00
Clifford Wolf
eb452ffb28
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-23 10:32:54 +02:00
Clifford Wolf
ddc1761f1a
Add "make coverage"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-27 14:22:21 +02:00
Clifford Wolf
4d269f9b25
Merge pull request #610 from udif/udif_specify_round2
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More specify/endspecify fixes
2018-08-23 14:43:25 +02:00
Udi Finkelstein
042b3074f8
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
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This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
2018-08-23 15:26:02 +03:00
Udi Finkelstein
fbfc677df3
Fixed all known specify/endspecify issues, without breaking 'make test'.
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Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
2018-08-20 17:27:45 +03:00
Udi Finkelstein
95241c8f4d
Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v ,
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(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
2018-08-20 00:08:08 +03:00
Udi Finkelstein
28cfc75a90
A few minor enhancements to specify block parsing.
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Just remember specify blocks are parsed but ignored.
2018-08-15 20:14:52 +03:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
Clifford Wolf
d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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Detect illegal port declaration, e.g input/output/inout keyword must …
2018-08-15 13:14:23 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Henner Zeller
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
Henner Zeller
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
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Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
Udi Finkelstein
8b7580b0a1
Detect illegal port declaration, e.g input/output/inout keyword must be the first.
2018-06-06 22:27:25 +03:00
Udi Finkelstein
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Jim Paris
4a229e5b95
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
Jim Paris
872d8d49e9
Skip spaces around macro arguments
2018-05-17 00:06:49 -04:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Dan Gisselquist
e060375f23
Support more character literals
2018-05-03 12:35:01 +02:00
Clifford Wolf
2d7f3123f0
Add statement labels for immediate assertions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-13 11:52:28 +02:00
Clifford Wolf
66ffc99695
Allow "property" in immediate assertions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-12 14:28:28 +02:00
Clifford Wolf
5ea2c53604
Add read_verilog anyseq/anyconst/allseq/allconst attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 14:35:11 +02:00
Udi Finkelstein
6378e2cd46
First draft of Verilog parser support for specify blocks and parameters.
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The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
2018-03-27 14:34:00 +02:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
34005348b6
Bugfix in verilog_defaults argument parser
2017-12-24 17:21:37 +01:00
Clifford Wolf
777f2881d8
Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00
Clifford Wolf
5b6e52118c
Accept real-valued delay values
2017-11-18 10:01:30 +01:00
William D. Jones
abc5b4b8ce
Accommodate Windows-style paths during include-file processing.
2017-11-14 16:16:24 -05:00
Udi Finkelstein
72a08eca3d
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
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(Oreilly 'Flex & Bison' page 189)
2017-09-30 06:39:07 +03:00
Clifford Wolf
2c04d883b1
Minor coding style fix
2017-09-26 13:50:14 +02:00
Clifford Wolf
cb1d439d10
Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master
2017-09-26 13:48:13 +02:00
Clifford Wolf
2cc09161ff
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
2017-09-26 01:52:59 +02:00
combinatorylogic
64ca0be971
Adding support for string macros and macros with arguments after include
2017-09-21 18:25:02 +01:00
Clifford Wolf
26766da343
Add a paragraph about pre-defined macros to read_verilog help message
2017-07-21 14:34:53 +02:00
Clifford Wolf
8f8baccfde
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
2017-06-07 12:30:24 +02:00
Clifford Wolf
129984e115
Fix handling of Verilog ~& and ~| operators
2017-06-01 12:43:21 +02:00
Clifford Wolf
e91548b33e
Add support for localparam in module header
2017-04-30 17:20:30 +02:00
Clifford Wolf
f0db8ffdbc
Add support for `resetall compiler directive
2017-04-26 16:09:41 +02:00
Clifford Wolf
088f9c9cab
Fix verilog pre-processor for multi-level relative includes
2017-03-14 17:30:20 +01:00
Clifford Wolf
5b3b5ffc8c
Allow $anyconst, etc. in non-formal SV mode
2017-03-01 10:47:05 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
00dba4c197
Add support for SystemVerilog unique, unique0, and priority case
2017-02-23 16:33:19 +01:00
Clifford Wolf
34d4e72132
Added SystemVerilog support for ++ and --
2017-02-23 11:21:33 +01:00
Clifford Wolf
848062088c
Add checker support to verilog front-end
2017-02-09 13:51:44 +01:00
Clifford Wolf
ef4a28e112
Add SV "rand" and "const rand" support
2017-02-08 14:38:15 +01:00
Clifford Wolf
6abf79eb28
Further improve cover() support
2017-02-04 17:02:13 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
fea528280b
Add "enum" and "typedef" lexer support
2017-01-17 17:33:52 +01:00
Clifford Wolf
3886669ab6
Added "verilog_defines" command
2016-12-15 17:49:28 +01:00
Clifford Wolf
ecdc22b06c
Added support for macros as include file names
2016-11-28 14:50:17 +01:00
Clifford Wolf
c7f6fb6e17
Bugfix in "read_verilog -D NAME=VAL" handling
2016-11-28 14:45:05 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
1276c87a56
Added read_verilog -norestrict -assume-asserts
2016-08-26 23:35:27 +02:00
Clifford Wolf
4be4969bae
Improved verilog parser errors
2016-08-25 11:44:37 +02:00
Clifford Wolf
cd18235f30
Added SV "restrict" keyword
2016-08-24 15:30:08 +02:00
Clifford Wolf
7f755dec75
Fixed bug in parsing real constants
2016-08-06 13:16:23 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
Clifford Wolf
5b944ef11b
Fixed a verilog parser memory leak
2016-07-25 16:37:58 +02:00
Clifford Wolf
7a67add95d
Fixed parsing of empty positional cell ports
2016-07-25 12:48:03 +02:00
Clifford Wolf
9aae1d1e8f
No tristate warning message for "read_verilog -lib"
2016-07-23 11:56:53 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Ruben Undheim
545bcb37e8
Allow defining input ports as "input logic" in SystemVerilog
2016-06-20 20:16:37 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Clifford Wolf
060bf4819a
Small improvements in Verilog front-end docs
2016-05-20 16:21:35 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
5a09fa4553
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
Clifford Wolf
33c10350b2
Fixed Verilog parser fix and more similar improvements
2016-03-15 12:22:31 +01:00
Andrew Becker
81d4e9e7c1
Use left-recursive rule for cell_port_list in Verilog parser.
2016-03-15 12:03:40 +01:00
Clifford Wolf
35a6ad4cc1
Fixed typos in verilog_defaults help message
2016-03-10 11:14:51 +01:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
5308c1e02a
Fixed bug in verilog parser
2015-10-15 15:19:23 +02:00
Clifford Wolf
f13e387321
SystemVerilog also has assume(), added implicit -D FORMAL
2015-10-13 14:21:20 +02:00
Clifford Wolf
ba4cce9f19
Added support for "parameter" and "localparam" in global context
2015-10-07 14:59:08 +02:00
Clifford Wolf
e2e092b144
Added read_verilog -nodpi
2015-09-23 08:23:38 +02:00
Clifford Wolf
b845b77f86
Fixed support for $write system task
2015-09-23 07:10:56 +02:00
Clifford Wolf
a3a13cce32
Fixed detection of "task foo(bar);" syntax error
2015-09-22 21:34:21 +02:00
Clifford Wolf
4b8200eb49
Fixed segfault on invalid verilog constant 1'b_
2015-09-22 08:13:09 +02:00
Clifford Wolf
a7ab9172f9
Small corrections to const2ast warning messages
2015-08-17 16:22:53 +02:00
Florian Zeitz
0491042849
Check base-n literals only contain valid digits
2015-08-17 15:37:33 +02:00
Florian Zeitz
64ccbf8510
Warn on literals exceeding the specified bit width
2015-08-17 15:27:35 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
0350074819
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
45ee2ba3b8
Fixed handling of [a-fxz?] in decimal constants
2015-08-11 11:32:37 +02:00
Marcus Comstedt
c836faae3e
Add -noautowire option to verilog frontend
2015-08-01 12:16:54 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
7ff802e199
Verilog front-end: define `BLACKBOX in -lib mode
2015-04-19 21:30:46 +02:00
Clifford Wolf
a923a63a89
Ignore celldefine directive in verilog front-end
2015-03-25 19:46:12 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
dc1a0f06fc
Parser support for complex delay expressions
2015-02-20 10:21:36 +01:00
Clifford Wolf
e0e6d130cd
YosysJS stuff
2015-02-19 13:36:54 +01:00
Clifford Wolf
7f1a1759d7
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
Clifford Wolf
ef151b0b30
Fixed handling of "//" in filenames in verilog pre-processor
2015-02-14 08:41:03 +01:00
Clifford Wolf
4f68a77e3f
Improved read_verilog support for empty behavioral statements
2015-02-10 12:17:29 +01:00
Clifford Wolf
df9d096a7d
Ignoring more system task and functions
2015-01-15 13:08:19 +01:00
Fabio Utzig
fff6f00b3c
Enable bison to be customized
2015-01-08 09:56:20 -02:00
Clifford Wolf
1bd67d792e
Define YOSYS and SYNTHESIS in preproc
2015-01-02 17:11:54 +01:00
Clifford Wolf
7751c491fb
Improved some warning messages
2014-12-27 03:40:27 +01:00
Clifford Wolf
1282a113da
Fixed supply0/supply1 with many wires
2014-12-11 13:56:20 +01:00
Clifford Wolf
76c83283c4
Fixed minor bug in parsing delays
2014-11-24 14:48:07 +01:00
Clifford Wolf
56c7d1e266
Fixed two minor bugs in constant parsing
2014-11-24 14:39:24 +01:00
Clifford Wolf
87333f3ae2
Added warning for use of 'z' constants in HDL
2014-11-14 19:59:50 +01:00
Clifford Wolf
4e5350b409
Fixed parsing of nested verilog concatenation and replicate
2014-11-12 19:10:35 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
a21481b338
Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
2014-10-30 14:01:02 +01:00
Clifford Wolf
f9c096eeda
Added support for task and function args in parentheses
2014-10-27 13:21:57 +01:00
Clifford Wolf
c5eb5e56b8
Re-introduced Yosys::readsome() helper function
...
(f.read() + f.gcount() made problems with lines > 16kB)
2014-10-23 10:58:36 +02:00
Clifford Wolf
3838856a9e
Print "SystemVerilog" in "read_verilog -sv" log messages
2014-10-16 10:31:54 +02:00
Clifford Wolf
f65e1c309f
Updated .gitignore file for ilang and verilog frontends
2014-10-15 01:14:38 +02:00
Clifford Wolf
c3e9922b5d
Replaced readsome() with read() and gcount()
2014-10-15 01:12:53 +02:00
William Speirs
fad0b0c506
Updated lexers & parsers to include prefixes
2014-10-15 00:48:19 +02:00
Clifford Wolf
8263f6a74a
Fixed win32 troubles with f.readsome()
2014-10-11 11:36:22 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
58367cd87a
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
2014-08-23 15:14:58 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
e218f0eacf
Added support for non-standard <plugin>:<c_name> DPI syntax
2014-08-22 14:30:29 +02:00
Clifford Wolf
6c5cafcd8b
Added support for DPI function with different names in C and Verilog
2014-08-21 17:22:04 +02:00
Clifford Wolf
7bfc4ae120
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
Clifford Wolf
38addd4c67
Added support for global tasks and functions
2014-08-21 12:42:28 +02:00
Clifford Wolf
640d9fc551
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
Clifford Wolf
6d56172c0d
Fixed line numbers when using here-doc macros
2014-08-14 22:26:30 +02:00
Clifford Wolf
f53984795d
Added support for non-standard """ macro bodies
2014-08-13 13:03:38 +02:00
Clifford Wolf
2dc3333734
Also allow "module foobar(input foo, output bar, ...);" syntax
2014-08-07 16:41:27 +02:00
Clifford Wolf
d259abbda2
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:52:54 +02:00
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
Clifford Wolf
b5a3419ac2
Added support for non-standard "module mod_name(...);" syntax
2014-08-04 15:40:07 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
7daad40ca4
Fixed counting verilog line numbers for "// synopsys translate_off" sections
2014-07-30 20:18:48 +02:00
Clifford Wolf
e605af8a49
Fixed Verilog pre-processor for files with no trailing newline
2014-07-29 20:14:25 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
ee8ad72fd9
fixed parsing of constant with comment between size and value
2014-07-02 06:27:04 +02:00
Clifford Wolf
0c4c79c4c6
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
2014-06-16 15:02:40 +02:00
Clifford Wolf
7f57bc8385
Improved parsing of large integer constants
2014-06-15 08:48:17 +02:00
Clifford Wolf
9bd7d5c468
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
Clifford Wolf
7ef0da32cd
Added Verilog lexer and parser support for real values
2014-06-13 11:29:23 +02:00
Clifford Wolf
482d9208aa
Added read_verilog -sv options, added support for bit, logic,
...
allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
5281562d0e
made the generate..endgenrate keywords optional
2014-06-06 23:05:01 +02:00
Clifford Wolf
b5cd7a0179
added while and repeat support to verilog parser
2014-06-06 17:40:04 +02:00
Clifford Wolf
f9c1cd5edb
Improved error message for options after front-end filename arguments
2014-06-04 09:10:50 +02:00
Clifford Wolf
7188542155
Fixed clang -Wdeprecated-register warnings
2014-04-20 14:28:23 +02:00
Clifford Wolf
a1be4816d6
Replaced depricated %name-prefix= bison directive
2014-04-20 14:22:11 +02:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Clifford Wolf
9992026a8d
Added support for `line compiler directive
2014-03-11 14:06:57 +01:00
Clifford Wolf
02e6f2c5be
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
Clifford Wolf
7d7e068dd1
Added a warning note about error reporting to read_verilog help message
2014-02-16 20:20:25 +01:00
Clifford Wolf
cd9e8741a7
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
Clifford Wolf
007bdff55d
Added support for functions returning integer
2014-02-12 23:29:54 +01:00
Clifford Wolf
aa8e754ae5
Added read_verilog -setattr
2014-02-05 11:22:10 +01:00
Clifford Wolf
cdd6e11af5
Added support for blanks after -I and -D in read_verilog
2014-02-02 13:06:21 +01:00
Clifford Wolf
d06258f74f
Added constant size expression support of sized constants
2014-02-01 13:50:23 +01:00
Clifford Wolf
375c4dddc1
Added read_verilog -icells option
2014-01-29 00:59:28 +01:00
Clifford Wolf
0b47d907d3
Fixed handling of unsized constants in verilog frontend
2014-01-24 15:05:24 +01:00
Clifford Wolf
9a1eb45c75
Added Verilog parser support for asserts
2014-01-19 04:18:22 +01:00
Clifford Wolf
13359d65ba
Fixed parsing of verilog macros at end of line
2014-01-18 19:22:20 +01:00
Clifford Wolf
6170cfe9cd
Added verilog_defaults command
2014-01-17 17:22:29 +01:00
Clifford Wolf
1dcbba1abf
Fixed parsing of non-arg macro calls followed by "("
2013-12-27 16:25:27 +01:00
Clifford Wolf
72026a934e
Fixed parsing of macros with no arguments and expansion text starting with "("
2013-12-27 15:05:52 +01:00
Clifford Wolf
ecc30255ba
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
Clifford Wolf
fbd06a1afc
Added elsif preproc support
2013-12-18 13:41:36 +01:00
Clifford Wolf
921064c200
Added support for macro arguments
2013-12-18 13:21:02 +01:00
Clifford Wolf
5c39948ead
Added AstNode::mkconst_str API
2013-12-05 12:53:49 +01:00
Clifford Wolf
4a4a3fc337
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
Clifford Wolf
507c63d112
Added support for local regs in named blocks
2013-12-04 09:10:16 +01:00
Clifford Wolf
7d9a90396d
Added verilog frontend -ignore_redef option
2013-11-24 19:57:42 +01:00
Clifford Wolf
1de12e1efc
Improved handling of initialized registers
2013-11-23 16:26:59 +01:00
Clifford Wolf
295e352ba6
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
Clifford Wolf
a362fd81ae
Fixed O(n^2) performance bug in verilog preprocessor
2013-11-22 14:08:43 +01:00
Clifford Wolf
e4429c480e
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
2013-11-22 12:46:02 +01:00
Clifford Wolf
92035fb38e
Implemented indexed part selects
2013-11-20 13:05:27 +01:00
Clifford Wolf
0f04738f40
Added "synthesis" in (synopsys|synthesis) comment support
2013-11-20 11:44:09 +01:00
Clifford Wolf
19dba2561e
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
Clifford Wolf
e340532ce5
Added init= attribute for fpga-style reset values
2013-11-20 01:49:37 +01:00
Clifford Wolf
0dfdbd991a
Fixed parsing of module arguments when one type is used for many args
2013-11-19 20:35:31 +01:00
Clifford Wolf
63060dcd2e
Fixed parsing of "parameter integer"
2013-11-13 15:30:23 +01:00
Clifford Wolf
f050c40519
Various fixes for correct parameter support
2013-11-07 10:02:11 +01:00
Clifford Wolf
23cf23418c
Fixed handling of boolean attributes (frontends)
2013-10-24 11:20:13 +02:00
Clifford Wolf
eae43e2db4
Fixed handling of boolean attributes (kernel)
2013-10-24 10:59:27 +02:00
Johann Glaser
f352205635
fixed Verilog parser filename and line numbering issue with include files
2013-08-21 09:20:59 +02:00
Johann Glaser
a99c224157
Added support for include directories with the new '-I' argument of the
...
'read_verilog' command
2013-08-20 15:48:16 +02:00
Johann Glaser
6c4cbc03c2
Added support for notif0/notif1 primitives
2013-08-20 11:23:59 +02:00
Clifford Wolf
8656b1c08f
Added support for bufif0/bufif1 primitives
2013-08-19 19:50:04 +02:00
Clifford Wolf
4214561890
Improved ast dumping (ast/verilog frontend)
2013-08-19 19:49:14 +02:00
Clifford Wolf
00a6c1d9a5
Major redesign of expr width/sign detecion (verilog/ast frontend)
2013-07-09 14:31:57 +02:00
Clifford Wolf
56432a920f
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
Clifford Wolf
0c6ffc4c65
More fixes for bugs found using xsthammer
2013-06-13 11:18:45 +02:00
Clifford Wolf
4b311b7b99
Further improved and extended xsthammer
2013-06-11 19:49:35 +02:00
Clifford Wolf
db98a18edb
Enabled AST/Verilog front-end optimizations per default
2013-06-10 13:19:04 +02:00
Clifford Wolf
46fbe9d262
Added SAT generator and simple sat_solve command
2013-06-07 13:59:13 +02:00
Johann Glaser
10a195c0a1
added option '-Dname[=definition]' to command 'read_verilog'
2013-05-19 17:07:52 +02:00
Clifford Wolf
b56e06d2f5
Added support for verilog === operator
2013-05-07 14:35:40 +02:00
Clifford Wolf
161565be10
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
2013-03-31 11:19:11 +02:00
Clifford Wolf
7bfc7b61a8
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
Clifford Wolf
7a99349de4
Improvements and bugfixes for generate blocks with local signals
2013-03-26 11:31:34 +01:00
Clifford Wolf
df9753d398
Added mem2reg option to verilog frontend
2013-03-24 11:13:32 +01:00
Clifford Wolf
e45d1c8865
Tiny fixes to verilog parser
2013-03-23 18:54:31 +01:00
Clifford Wolf
8a6b0a3520
Added help messages to ilang and verilog frontends
2013-03-01 08:03:00 +01:00
Clifford Wolf
a321a5c412
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
Clifford Wolf
4f0c2862a0
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
Clifford Wolf
6d1502b948
Added support for "always @(*)"
2013-01-16 17:32:11 +01:00
Clifford Wolf
6543917fb8
added .gitignore files
2013-01-05 11:19:11 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00