mirror of https://github.com/YosysHQ/yosys.git
Improve read_verilog debug output capabilities
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
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8c0740bcf7
commit
9b0e7af6d7
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@ -45,7 +45,7 @@ namespace AST {
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// instantiate global variables (private API)
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namespace AST_INTERNAL {
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bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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AstNode *current_ast, *current_ast_mod;
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std::map<std::string, AstNode*> current_scope;
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@ -562,7 +562,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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case AST_CONCAT:
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fprintf(f, "{");
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for (auto child : children) {
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for (int i = GetSize(children)-1; i >= 0; i--) {
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auto child = children[i];
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if (!first)
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fprintf(f, ", ");
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child->dumpVlog(f, "");
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@ -926,23 +927,28 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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ast_before_simplify = ast->clone();
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if (flag_dump_ast1) {
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log("Dumping Verilog AST before simplification:\n");
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log("Dumping AST before simplification:\n");
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ast->dumpAst(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (flag_dump_vlog1) {
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log("Dumping Verilog AST before simplification:\n");
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ast->dumpVlog(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (!defer)
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{
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while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
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if (flag_dump_ast2) {
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log("Dumping Verilog AST after simplification:\n");
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log("Dumping AST after simplification:\n");
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ast->dumpAst(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (flag_dump_vlog) {
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log("Dumping Verilog AST (as requested by dump_vlog option):\n");
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if (flag_dump_vlog2) {
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log("Dumping Verilog AST after simplification:\n");
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ast->dumpVlog(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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@ -1016,14 +1022,15 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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}
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// create AstModule instances for all modules in the AST tree and add them to 'design'
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
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{
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current_ast = ast;
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flag_dump_ast1 = dump_ast1;
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flag_dump_ast2 = dump_ast2;
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flag_no_dump_ptr = no_dump_ptr;
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flag_dump_vlog = dump_vlog;
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flag_dump_vlog1 = dump_vlog1;
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flag_dump_vlog2 = dump_vlog2;
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flag_dump_rtlil = dump_rtlil;
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flag_nolatches = nolatches;
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flag_nomeminit = nomeminit;
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@ -1357,7 +1364,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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current_ast = NULL;
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flag_dump_ast1 = false;
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flag_dump_ast2 = false;
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flag_dump_vlog = false;
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flag_dump_vlog1 = false;
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flag_dump_vlog2 = false;
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flag_nolatches = nolatches;
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flag_nomeminit = nomeminit;
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flag_nomem2reg = nomem2reg;
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@ -282,7 +282,7 @@ namespace AST
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};
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
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bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
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// parametric modules are supported directly by the AST library
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@ -81,6 +81,9 @@ struct VerilogFrontend : public Frontend {
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log(" -assert-assumes\n");
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log(" treat all assume() statements like assert() statements\n");
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log("\n");
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log(" -debug\n");
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log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
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log("\n");
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log(" -dump_ast1\n");
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log(" dump abstract syntax tree (before simplification)\n");
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log("\n");
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@ -90,7 +93,10 @@ struct VerilogFrontend : public Frontend {
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log(" -no_dump_ptr\n");
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log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" -dump_vlog1\n");
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log(" dump ast as Verilog code (before simplification)\n");
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log("\n");
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log(" -dump_vlog2\n");
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log(" dump ast as Verilog code (after simplification)\n");
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log("\n");
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log(" -dump_rtlil\n");
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@ -197,7 +203,8 @@ struct VerilogFrontend : public Frontend {
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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bool flag_no_dump_ptr = false;
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bool flag_dump_vlog = false;
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bool flag_dump_vlog1 = false;
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bool flag_dump_vlog2 = false;
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bool flag_dump_rtlil = false;
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bool flag_nolatches = false;
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bool flag_nomeminit = false;
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@ -258,6 +265,14 @@ struct VerilogFrontend : public Frontend {
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assert_assumes_mode = true;
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continue;
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}
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if (arg == "-debug") {
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flag_dump_ast1 = true;
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flag_dump_ast2 = true;
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flag_dump_vlog1 = true;
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flag_dump_vlog2 = true;
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frontend_verilog_yydebug = true;
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continue;
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}
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if (arg == "-dump_ast1") {
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flag_dump_ast1 = true;
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continue;
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@ -270,8 +285,12 @@ struct VerilogFrontend : public Frontend {
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flag_no_dump_ptr = true;
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continue;
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}
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if (arg == "-dump_vlog") {
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flag_dump_vlog = true;
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if (arg == "-dump_vlog1") {
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flag_dump_vlog1 = true;
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continue;
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}
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if (arg == "-dump_vlog2") {
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flag_dump_vlog2 = true;
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continue;
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}
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if (arg == "-dump_rtlil") {
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@ -410,7 +429,7 @@ struct VerilogFrontend : public Frontend {
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if (flag_nodpi)
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error_on_dpi_function(current_ast);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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delete lexin;
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