riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #562 from udif/pr_fix_illegal_port_decl 

Detect illegal port declaration, e.g input/output/inout keyword must …
This commit is contained in:
Clifford Wolf 2018-08-15 13:14:23 +02:00 committed by GitHub
parent 1dd156f516 8b7580b0a1
commit d71529baa1
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
frontends/verilog/verilog_parser.y
View File

@ -376,9 +376,10 @@ wire_type:
};
wire_type_token_list:
wire_type_token | wire_type_token_list wire_type_token;
wire_type_token | wire_type_token_list wire_type_token |
wire_type_token_io ;
wire_type_token:
wire_type_token_io:
TOK_INPUT {
astbuf3->is_input = true;
} |
@ -388,7 +389,9 @@ wire_type_token:
TOK_INOUT {
astbuf3->is_input = true;
astbuf3->is_output = true;
} |
};
wire_type_token:
TOK_WIRE {
} |
TOK_REG {