mirror of https://github.com/YosysHQ/yosys.git
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
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408077769f
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@ -44,7 +44,7 @@ namespace AST {
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// instanciate global variables (private API)
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namespace AST_INTERNAL {
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bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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AstNode *current_ast, *current_ast_mod;
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std::map<std::string, AstNode*> current_scope;
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@ -267,10 +267,12 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
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std::string type_name = type2str(type);
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fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
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if (id2ast)
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fprintf(f, " [%p -> %p]", this, id2ast);
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else
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fprintf(f, " [%p]", this);
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if (!flag_no_dump_ptr) {
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if (id2ast)
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fprintf(f, " [%p -> %p]", this, id2ast);
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else
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fprintf(f, " [%p]", this);
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}
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if (!str.empty())
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fprintf(f, " str='%s'", str.c_str());
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@ -1008,12 +1010,13 @@ static AstModule* process_module(AstNode *ast, bool defer)
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}
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// create AstModule instances for all modules in the AST tree and add them to 'design'
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
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{
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current_ast = ast;
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flag_dump_ast1 = dump_ast1;
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flag_dump_ast2 = dump_ast2;
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flag_no_dump_ptr = no_dump_ptr;
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flag_dump_vlog = dump_vlog;
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flag_dump_rtlil = dump_rtlil;
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flag_nolatches = nolatches;
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@ -274,7 +274,7 @@ namespace AST
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};
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
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bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
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// parametric modules are supported directly by the AST library
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@ -305,7 +305,7 @@ namespace AST
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namespace AST_INTERNAL
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{
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// internal state variables
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extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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extern AST::AstNode *current_ast, *current_ast_mod;
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extern std::map<std::string, AST::AstNode*> current_scope;
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@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend {
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log(" -dump_ast2\n");
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log(" dump abstract syntax tree (after simplification)\n");
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log("\n");
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log(" -no_dump_ptr\n");
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log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" dump ast as Verilog code (after simplification)\n");
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log("\n");
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@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend {
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{
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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bool flag_no_dump_ptr = false;
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bool flag_dump_vlog = false;
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bool flag_dump_rtlil = false;
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bool flag_nolatches = false;
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@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend {
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flag_dump_ast2 = true;
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continue;
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}
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if (arg == "-no_dump_ptr") {
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flag_no_dump_ptr = true;
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continue;
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}
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if (arg == "-dump_vlog") {
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flag_dump_vlog = true;
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continue;
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@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend {
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if (flag_nodpi)
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error_on_dpi_function(current_ast);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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delete lexin;
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