mirror of https://github.com/YosysHQ/yosys.git
Add "verific -work" help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -1706,11 +1706,18 @@ struct VerificPass : public Pass {
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log("\n");
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log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
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log("\n");
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log("\n");
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log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
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log("\n");
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log("Load the specified VHDL files into Verific.\n");
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log("\n");
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log("\n");
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log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
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log("\n");
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log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
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log("(default library when -work is not present: \"work\")\n");
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log("\n");
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log("\n");
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log(" verific -vlog-incdir <directory>..\n");
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log("\n");
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log("Add Verilog include directories.\n");
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