mirror of https://github.com/YosysHQ/yosys.git
Initial implementation of elaboration system tasks
(IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
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@ -154,6 +154,7 @@ std::string AST::type2str(AstNodeType type)
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X(AST_GENIF)
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X(AST_GENCASE)
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X(AST_GENBLOCK)
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X(AST_TECALL)
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X(AST_POSEDGE)
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X(AST_NEGEDGE)
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X(AST_EDGE)
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@ -137,7 +137,8 @@ namespace AST
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AST_GENIF,
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AST_GENCASE,
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AST_GENBLOCK,
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AST_TECALL,
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AST_POSEDGE,
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AST_NEGEDGE,
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AST_EDGE,
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@ -233,6 +234,7 @@ namespace AST
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bool mem2reg_check(pool<AstNode*> &mem2reg_set);
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void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);
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void meminfo(int &mem_width, int &mem_size, int &addr_bits);
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bool check_elab_tasks(void);
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// additional functionality for evaluating constant functions
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struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };
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@ -856,6 +856,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_GENVAR:
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case AST_GENFOR:
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case AST_GENBLOCK:
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case AST_TECALL:
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case AST_GENIF:
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case AST_GENCASE:
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case AST_PACKAGE:
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@ -1146,7 +1146,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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if (type == AST_GENFOR) {
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for (size_t i = 0; i < buf->children.size(); i++) {
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buf->children[i]->simplify(false, false, false, stage, -1, false, false);
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if (!buf->children[i]->check_elab_tasks())
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buf->children[i]->simplify(false, false, false, stage, -1, false, false);
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current_ast_mod->children.push_back(buf->children[i]);
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}
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} else {
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@ -1261,7 +1262,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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}
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for (size_t i = 0; i < buf->children.size(); i++) {
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buf->children[i]->simplify(false, false, false, stage, -1, false, false);
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if (!buf->children[i]->check_elab_tasks())
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buf->children[i]->simplify(false, false, false, stage, -1, false, false);
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current_ast_mod->children.push_back(buf->children[i]);
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}
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@ -1340,7 +1342,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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}
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for (size_t i = 0; i < buf->children.size(); i++) {
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buf->children[i]->simplify(false, false, false, stage, -1, false, false);
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if (!buf->children[i]->check_elab_tasks())
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buf->children[i]->simplify(false, false, false, stage, -1, false, false);
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current_ast_mod->children.push_back(buf->children[i]);
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}
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@ -2969,6 +2972,44 @@ static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> &
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}
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}
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// handle $info(), $warning(), $error(), $fatal()
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// we don't do that in simplify() because we don't know
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bool AstNode::check_elab_tasks(void)
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{
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if (type == AST_TECALL) {
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int sz = children.size();
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if (str == "$info") {
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if (sz > 0)
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log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str());
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else
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log_file_info(filename, linenum, "\n");
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} else if (str == "$warning") {
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if (sz > 0)
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log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str());
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else
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log_file_warning(filename, linenum, "\n");
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} else if (str == "$error") {
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if (sz > 0)
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log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str());
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else
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log_file_error(filename, linenum, "\n");
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} else if (str == "$fatal") {
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// TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
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// if no parameter is given, default value is 1
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// dollar_finish(sz ? children[0] : 1);
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// perhaps create & use log_file_fatal()
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if (sz > 0)
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log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str());
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else
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log_file_error(filename, linenum, "FATAL.\n");
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} else {
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log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str());
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}
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return true;
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}
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return false;
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}
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// find memories that should be replaced by registers
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void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
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dict<AstNode*, uint32_t> &mem2reg_candidates, dict<AstNode*, uint32_t> &proc_flags, uint32_t &flags)
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@ -301,6 +301,11 @@ supply1 { return TOK_SUPPLY1; }
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return TOK_ID;
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}
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"$"(info|warning|error|fatal) {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_ELAB_TASK;
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}
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"$signed" { return TOK_TO_SIGNED; }
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"$unsigned" { return TOK_TO_UNSIGNED; }
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@ -105,7 +105,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
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bool boolean;
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}
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%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL
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%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL TOK_ELAB_TASK
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%token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
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%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
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%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
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@ -1869,6 +1869,15 @@ gen_stmt:
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if ($6 != NULL)
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delete $6;
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ast_stack.pop_back();
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} |
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TOK_ELAB_TASK {
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AstNode *node = new AstNode(AST_TECALL);
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node->str = *$1;
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delete $1;
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ast_stack.back()->children.push_back(node);
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ast_stack.push_back(node);
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} opt_arg_list ';'{
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ast_stack.pop_back();
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};
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gen_stmt_block:
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@ -278,6 +278,17 @@ void log_file_warning(const std::string &filename, int lineno,
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va_end(ap);
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}
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void log_file_info(const std::string &filename, int lineno,
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const char *format, ...)
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{
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va_list ap;
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va_start(ap, format);
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std::string prefix = stringf("%s:%d: Info: ",
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filename.c_str(), lineno);
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logv_warning_with_prefix(prefix.c_str(), format, ap);
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va_end(ap);
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}
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YS_ATTRIBUTE(noreturn)
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static void logv_error_with_prefix(const char *prefix,
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const char *format, va_list ap)
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@ -80,6 +80,7 @@ void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
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// Log with filename to report a problem in a source file.
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void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
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void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
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void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
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YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
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@ -0,0 +1,30 @@
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module test;
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localparam X=1;
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genvar i;
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generate
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if (X == 1)
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$info("X is 1");
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if (X == 1)
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$warning("X is 1");
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else
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$error("X is not 1");
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case (X)
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1: $info("X is 1 in a case statement");
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endcase
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//case (X-1)
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// 1: $warn("X is 2");
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// default: $warn("X might be anything in a case statement");
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//endcase
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for (i = 0; i < 3; i = i + 1)
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begin
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case(i)
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0: $info;
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1: $warning;
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default: $info("default case statemnent");
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endcase
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end
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$info("This is a standalone $info(). Next $info has no parameters");
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$info;
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endgenerate
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endmodule
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@ -0,0 +1 @@
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read_verilog -sv elab_sys_tasks.sv
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