1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
4c7f4bd82f
ahoy nice
2021-02-09 17:38:19 -05:00
2b51b36dd6
[Test] Now use the super LUT arch in the test case
2021-02-09 15:27:44 -07:00
56284059de
[Test] Add a test case for a super LUT
2021-02-09 15:25:32 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
71c76df063
default to ns for time unit -- synopsys dc whines
2021-02-09 17:08:38 -05:00
6bb2e29f17
default to ns for time unit -- synopsys dc whines
2021-02-09 17:04:52 -05:00
87c69460df
what is going on
2021-02-09 11:33:08 -05:00
cc74c6268a
trying fix chan width
2021-02-09 11:28:19 -05:00
95fe4d7dae
adding dff synth
2021-02-09 10:34:54 -05:00
b14b5f975d
adding sweep for W
2021-02-09 08:48:25 -05:00
d7967da328
bugfix in alt
2021-02-08 23:04:00 -05:00
485708423c
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
cf154d8bb9
no need for dff*, but need tap_buf4
2021-02-08 22:29:55 -05:00
e14c0bf0c4
no need for dff*, but need tap_buf4
2021-02-08 22:28:42 -05:00
45437fbc46
no need for dff*, but need tap_buf4
2021-02-08 22:27:57 -05:00
853bf8af43
typos fixed;
2021-02-08 22:03:14 -05:00
d040ba569c
merge for consideration;
2021-02-08 21:29:34 -05:00
94f858fcde
merge for consideration;
2021-02-08 21:27:01 -05:00
0c6d27cf7e
merge for consideration;
2021-02-08 21:26:48 -05:00
b4185f7e8c
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
2021-02-08 21:11:30 -05:00
2344cdcabc
merge
2021-02-08 21:11:28 -05:00
1ce94040da
Merge pull request #221 from lnis-uofu/flow_dev
...
[Flow] Support multi-user environment for running task
2021-02-08 12:43:57 -07:00
80a4872ba0
Merge pull request #222 from lnis-uofu/gg_cleanup
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[Flow] ACE is optional during flow script, only runs when power estimation is on
2021-02-08 10:08:47 -07:00
ede5f8ed58
[Flow] Support multi-user enviroment for running task
2021-02-07 22:11:04 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
ee14c15e58
Merge pull request #212 from lnis-uofu/soft_adder_lut_support
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Support overloading LUT bitstream from attributes in .eblif file format
2021-02-04 21:55:02 -07:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
224bf6c686
Merge branch 'master' into dev
2021-02-04 17:21:15 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
6cdc31f073
[Flow] ACE is optional duign flow script
2021-02-03 19:07:48 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
df4a397470
[Cleanup] Removed deadcode
2021-02-03 10:35:14 -07:00
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
31441c0b64
[Test] Deploy adder_8 to soft adder test
2021-02-03 09:26:38 -07:00
05d63567d0
[Benchmark] Use latest adder eblif file
2021-02-03 09:21:38 -07:00
ebe66dea35
Bumping up latest yosys changes related to adder tech mapping
2021-02-03 14:30:06 +05:30
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
8e36ed1ab6
[Test] Update task configuration to use and2 eblif
2021-02-02 15:01:15 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
5e2847bc41
[Test] Update test case to use eblif file
2021-02-02 09:33:41 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
d3397f6936
[Script] Remove activity from bitstream setting example script
2021-02-02 09:25:36 -07:00
9ff5e7926b
[Test] Update test case to use the adder benchmark
2021-02-02 09:24:39 -07:00
7f14dfbe87
[Script] Add example script to use bitstream setting
2021-02-02 09:18:08 -07:00
04594cb7ab
[Test] Adapt bitstream annotatin file to parser's requirement
2021-02-01 17:38:36 -07:00
280c9620aa
[Test] Add an example bitstream annotation file
2021-02-01 16:01:21 -07:00
a6354fab7c
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
df88e2adc0
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
2021-02-01 14:26:11 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
b215b868c1
[HDL] Bug fix in HDL netlist due to port name mismatching
2021-02-01 11:35:25 -07:00
e4abe263c3
[Arch] Bug fix
2021-02-01 11:29:27 -07:00
fb05e1a938
[Arch] bug fix due to using openfpga cell library
2021-02-01 11:27:21 -07:00
940dce469a
[Test] Bug fix for test case configuration
2021-02-01 11:19:47 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
af630dab1e
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
2021-02-01 10:53:38 -07:00
9cce411eda
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
0eb949b85a
[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
2021-02-01 10:34:32 -07:00
e0e2506e32
[HDL] Remove redundant comments
2021-02-01 10:33:08 -07:00
39543f7945
[HDL] Add carry mux2 to cell library
2021-02-01 10:23:46 -07:00
6ede799c16
[Arch] Add openfpga architecture for the QLSOFA
2021-02-01 10:15:35 -07:00
df05911d24
Merge branch 'master' into soft_adder_lut_support
2021-02-01 10:02:05 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
a70725b4be
Merge branch 'master' into dev
2021-01-29 11:41:40 -07:00
8b74947737
[Script] Now multi-clock openfpga shell script no longer needs activity file
2021-01-29 11:40:33 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
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* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
0b82b6439b
[Regression] Upgraded runtime enviroment to python3.8
2021-01-26 16:40:45 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
3fdd5ae8b3
[Script] Use pin constraints in template script
2021-01-19 17:42:25 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
12e0efd03e
[Script] Add an example openfpga script to use repack design constraints
2021-01-17 10:33:56 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
89f9d24d32
[Flow] Update simulation settings for multiple clock to allow unique clock port name
2021-01-15 10:35:43 -07:00
dbed04b53b
[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
2021-01-14 15:42:21 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
923f3a3401
[Flow] Add an example simulation settings for a 4-clock FPGA fabric
2021-01-13 17:29:39 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
c5a2027f36
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
2021-01-13 15:41:48 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
ccf3e037ff
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
2021-01-13 13:31:06 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
2f1aceda67
[Doc] Update documentation about architecture naming rules
2021-01-12 18:01:24 -07:00
9fa49c401c
[Arch] Add openfpga architecture which uses 4 global clocks
2021-01-12 18:00:22 -07:00
16b4e89326
[Doc] Update documentation for VPR architectures
2021-01-12 17:57:40 -07:00
7ccdff4543
[Arch] Add an architecture using 4 clocks
2021-01-12 17:55:57 -07:00
3790f2c26a
[Benchmark] Add 2-clock micro benchmark
2021-01-12 17:48:52 -07:00
a0b9f2b40d
Merge pull request #170 from lnis-uofu/dev
...
Extended Support on Defining Global Ports from Physical Tile Ports
2021-01-11 10:02:31 -07:00
e58e1e86c2
[Test] Update test case to use new shell script
2021-01-10 11:09:10 -07:00
18d2a8ce19
[Flow] Add new script for fixed device layout using global tile clock
2021-01-10 11:08:02 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
1c68e43acf
[Test] Add new test case for registerable I/O architecture
2021-01-10 11:00:21 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
dfb3e32147
[Arch] Add openfpga archiecture for registerable I/O
2021-01-10 10:54:41 -07:00
853e7b1a40
[Arch] Add vpr architecture where I/O can be either combinational or registered
2021-01-10 10:54:09 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
6521aa2e7a
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 10:27:59 -07:00
4412bbd084
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 10:21:30 -07:00
0b74575606
[Arch] Update arch using global reset tile port
2021-01-09 18:04:55 -07:00
7b24da267a
[Arch] Remove port size XML syntax
2021-01-09 16:30:46 -07:00
9f12b25a24
[Arch] Add port size to global port defined thru tile annotation
2021-01-09 16:23:28 -07:00
0f5f0a3527
[Arch] Add x,y coordinates to global port definition
2021-01-09 15:50:09 -07:00
a14a56772a
[Arch] Introduce new XML syntax for global port in tile annotation
2021-01-09 15:48:42 -07:00
8a5741b1ae
Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
2021-01-08 07:08:24 -08:00
a813c9016b
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
2021-01-04 17:39:13 -07:00
06af30ef10
[Test] Add test case for the SCFF usage in configuration chain
2021-01-04 17:30:19 -07:00
709ee1b842
[HDL] Update dff netlist for SCFF used in configuration chain
2021-01-04 17:17:35 -07:00
c97a92d628
[Arch] Patch openfpga architecture for ccff circuit model port requirement
2021-01-04 17:15:50 -07:00
294ad97d38
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
2021-01-04 14:56:49 -07:00
722a9bcf63
[HDL] Add scan-chain DFF cell with configuration enable signal
2021-01-04 14:31:26 -07:00
2484721a45
Updating write_verilog_testbench by removing option explicit_port_mapping
2020-12-22 22:17:50 -08:00
3c9e4919b4
Updating variable name in ys to call BLIF output file.
2020-12-18 03:18:46 -08:00
1f994319fd
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
2020-12-16 04:19:56 -08:00
891e2f8aa3
Adding arch xml from SOFA repo. Also updating the script with its file location
2020-12-16 04:14:18 -08:00
0ee3efb306
Adding a testcase to run yosys quicklogic flow
2020-12-10 02:41:43 -08:00
6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
...
Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
6001da3a40
[Arch] Bug fix in tileable I/O arch example
2020-12-04 17:56:54 -07:00
1d0bdcfeca
[Arch] Simplify the grid layout modeling
2020-12-04 17:38:44 -07:00
1c3f625e41
[Arch] Force empty tiles at corners for tileable I/O arch example
2020-12-04 17:11:06 -07:00
0cb8457e21
[Test] Add test case for tileable I/O
2020-12-04 16:02:47 -07:00
186eb0f0a4
[Arch] Add tileable I/O architecture example
2020-12-04 15:59:39 -07:00
289d9d2169
[Bugfix] Honors yosys_tmpl parameter in flow script
2020-12-03 12:24:24 -07:00
412fb5bb31
[Arch] Bug fix due to valid default value parser
2020-12-02 17:51:50 -07:00
179b0ce304
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
2020-11-30 18:11:47 -07:00
c7604ab94f
[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
2020-11-30 18:02:00 -07:00
ff53d2c375
[HDL] Add new Scan-chain DFF cell
2020-11-30 17:54:10 -07:00
ad703ad85b
[HDL] Add new gpio cell with protection circuitry
2020-11-30 17:52:39 -07:00
27a480b5f8
[Test] arch name fix in the test case
2020-11-30 17:45:54 -07:00
7a0a3398d4
[Arch] Add new architecture to test global reset ports defined thru tile ports
2020-11-30 17:43:41 -07:00
a1d3b439d3
[Test] Add a new test case to define a global reset port from a global tile port
2020-11-30 17:19:12 -07:00
a60bd4d14a
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
7db030018c
[Bug] Fixed variable file location
2020-11-25 22:44:40 -07:00
b8559249dc
[Test] Bug fix in task configuration file
2020-11-25 22:23:27 -07:00
26e4db56ad
[Test] Add new test case for the native fracturable LUT4
2020-11-25 22:21:23 -07:00
17070c6405
[Doc] Update README in openfpga arch directory for native fracturable LUT design
2020-11-25 22:19:20 -07:00
tangxifan
Nachiket Kapre
Ganesh Gore
AurelienAlacchi
Lalit Sharma