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OpenFPGA
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790 Commits

Author SHA1 Message Date
tangxifan baf162e401 [Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification 2021-03-10 22:45:19 -07:00
tangxifan a6186db315 [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
tangxifan 7d07f5d8cb [Test] Update bitstream setting example with mode bit overwriting 2021-03-10 15:34:53 -07:00
tangxifan b42541d84e [Flow] Support multiple iterations in rewriting yosys scripts 2021-03-10 14:10:35 -07:00
tangxifan 90a00da1df [Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset' 2021-03-10 13:56:35 -07:00
tangxifan d21909ad6c [Test] Use custom rewriting script in lut_adder test 2021-03-10 13:48:20 -07:00
tangxifan 0e772bc3b4 [Script] Patch the yosys rewrite script to avoid existing blif outputs 2021-03-10 13:47:30 -07:00
tangxifan 7adb78b159 [Script] Add a template yosys script with rewriting at the end 2021-03-10 13:40:31 -07:00
tangxifan 035043d0d8 [Script] Revert to the state that post synthesis verilog is not required for yosys_vpr 2021-03-10 13:36:11 -07:00
tangxifan 5d46537b5b [Script] Allow users to specify custom post-synthesis verilog for simulation 2021-03-10 11:45:55 -07:00
tangxifan aafd87c3f9 [Flow] Update flow-run to support custom yosys rewrite scripts 2021-03-10 11:36:29 -07:00
tangxifan 2daa770319 [Arch] Update openfpga architecture to include quicklogic cell sim 2021-03-08 21:40:29 -07:00
tangxifan 812d8c950e [Script] Update quicklogic's script to output correct verilog file name 2021-03-08 21:39:44 -07:00
tangxifan 37aa42d305 [Test] Patch task configuration file for lut_adder_test to use correct rewrite script 2021-03-08 21:38:51 -07:00
tangxifan c53c41b7a5 [Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file 2021-03-08 21:09:23 -07:00
tangxifan 131643dcc0 [Flow] Bug fix for yosys rewrite function in openfpga flow-run script 2021-03-08 21:08:55 -07:00
ganeshgore b860722893
Fixed parameter ys_rewrite_params name bug 2021-03-08 10:34:39 -07:00
ganeshgore 52de55e7eb
Merge branch 'master' into ganesh_dev 2021-03-08 10:15:06 -07:00
tangxifan 906d2fa72d
Merge branch 'master' into shift_reg 2021-03-08 09:24:29 -07:00
Ganesh Gore 7a35811430 [Flow] Yosys rewrite support 2021-03-08 00:35:47 -07:00
Ganesh Gore 67cd9a69b7 [Flow] Extended yosys variable subtitution 2021-03-08 00:21:07 -07:00
Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification 2021-03-07 22:25:01 -08:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
Lalit Sharma 2b2acae757 Adding command to generate verilog file out of yosys run 2021-03-05 04:07:02 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
Lalit Sharma 0038496d9c Replacing -openfpga with -family qlf_k4n8 2021-02-28 21:08:47 -08:00
tangxifan b4b6ada06f [Script] Correct bugs in example scripts using default_net_type 2021-02-28 16:31:44 -07:00
tangxifan 86930d63d3 [Test] Deploy new test to CI 2021-02-28 16:18:46 -07:00
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
tangxifan 9f4d05da67 [Test] Bug fix for new test case 2021-02-28 16:11:30 -07:00
tangxifan 8cc2c7d924 [Script] Bug fix for default net type example script 2021-02-28 12:35:44 -07:00
tangxifan 6d419fed41 [Test] Deploy verilog default net wire type test case to CI 2021-02-28 12:33:48 -07:00
tangxifan 18a7041424 [Test] Add default net type test for explicit port mapping 2021-02-28 12:31:32 -07:00
tangxifan 0723b79bce [Script] Add example script for verilog default net type 2021-02-28 12:29:56 -07:00
tangxifan 27200e3daa [Test] Update regression test cases for fpga verilog 2021-02-28 12:24:36 -07:00
tangxifan ff29cc3dff [Test] Move tests to a test group 2021-02-28 12:23:35 -07:00
tangxifan 9cb1ca42fe [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
tangxifan ae05871b1f [Script] Remove default net type from an example script; Limit it to some test cases 2021-02-28 12:19:14 -07:00
tangxifan d7eb159726 [Script] Add default net type option to example openfpga shell scripts 2021-02-28 12:08:30 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 744d87cb4e [Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues 2021-02-26 09:34:52 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
tangxifan 4c2a88e27f [Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed 2021-02-24 11:51:10 -07:00
tangxifan 0ce9b66c75 [Arch] Add a dummy adder lut circuit model to support HDL simulation 2021-02-24 10:09:44 -07:00