tangxifan
|
3ac3eb4624
|
[test] adding more flavor to the L shape
|
2023-08-17 15:08:27 -07:00 |
|
tangxifan
|
85bc890009
|
[test] add a new test to validate comb options of group tile, group config block and L shape fabric
|
2023-08-17 14:52:30 -07:00 |
|
tangxifan
|
2f49c25f09
|
[test] updated
|
2023-08-11 21:19:06 -07:00 |
|
tangxifan
|
b155e660ee
|
[test] fixed a bug
|
2023-08-11 16:55:35 -07:00 |
|
tangxifan
|
253d5fa26c
|
[core] a new test to validate the L shape in homo geneous fpga
|
2023-08-11 13:05:46 -07:00 |
|
tangxifan
|
dc0eec8b81
|
[test] added a new test to validate L shapre
|
2023-08-11 12:49:38 -07:00 |
|
tangxifan
|
0e9cf6e909
|
[test] added a new testcase to validate heterogeneous fpga using group config block
|
2023-08-06 22:11:38 -07:00 |
|
tangxifan
|
3e33f262bc
|
[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
|
2023-08-06 18:59:24 -07:00 |
|
tangxifan
|
46b1de08c6
|
[test] fixed a bug
|
2023-08-05 22:07:46 -07:00 |
|
tangxifan
|
b7048d3dc8
|
[test] adding new tests to validate group config block
|
2023-08-03 22:30:41 -07:00 |
|
tangxifan
|
667c5f8944
|
[test] fixed a bug on the testcase
|
2023-07-27 22:02:28 -07:00 |
|
tangxifan
|
952e84fce1
|
[test] now heterogeneous testcases for tile modules pass
|
2023-07-27 20:30:32 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
65995d7c13
|
[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
|
2023-07-27 17:03:02 -07:00 |
|
tangxifan
|
46e58a56cb
|
[test] added a new test case to validate clock network when using the tile modules
|
2023-07-27 16:39:48 -07:00 |
|
tangxifan
|
81d699a723
|
[test] added a new testcase to validate carry chain connections in tile modules
|
2023-07-27 16:18:30 -07:00 |
|
tangxifan
|
e9f2adf3f9
|
[test] add a new testcase to validate carry chain connections when using tile modules
|
2023-07-27 16:06:43 -07:00 |
|
tangxifan
|
1ea8a33d4b
|
[test] add a new testcase to validate global tile connections on tile modules
|
2023-07-27 15:57:38 -07:00 |
|
tangxifan
|
a2848940df
|
[test] add a new testcase to ease debugging
|
2023-07-26 22:32:03 -07:00 |
|
tangxifan
|
5685fbd5e8
|
[test] adding a new test case to validate the tile modules on 4x4 fabric
|
2023-07-26 22:17:39 -07:00 |
|
tangxifan
|
bb837f4f79
|
[test] update golden netlists
|
2023-07-25 23:39:59 -07:00 |
|
tangxifan
|
0db4ef62e8
|
[test] add a new test for tile-based fabric: using preconfig testbenches
|
2023-07-25 15:48:14 -07:00 |
|
tangxifan
|
82fe63297a
|
[test] add a new test for top-left tile grouping
|
2023-07-19 11:22:36 -07:00 |
|
tangxifan
|
930d98f2af
|
[test] deploy new tests
|
2023-07-08 21:52:16 -07:00 |
|
tangxifan
|
51e1547634
|
[test] hotfix
|
2023-06-26 15:32:16 -07:00 |
|
tangxifan
|
270d6f933b
|
[test] add a new testcase to validate mock wrapper
|
2023-06-26 15:26:50 -07:00 |
|
tangxifan
|
919d6d8608
|
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
|
2023-06-25 22:49:51 -07:00 |
|
tangxifan
|
523e338d53
|
[test] debugging
|
2023-06-23 14:49:52 -07:00 |
|
tangxifan
|
962ba67e36
|
[test] adding new tests to validate fpga core wrapper naming rules
|
2023-06-23 14:47:21 -07:00 |
|
tangxifan
|
84edd41342
|
[test] fixed the bug in adder mapping
|
2023-06-20 17:09:31 -07:00 |
|
tangxifan
|
dba48fb171
|
[test] reworking adder mapping flow to validate carry chain mapping
|
2023-06-20 16:57:08 -07:00 |
|
tangxifan
|
efc9bf9907
|
[test] added new test case to validate bitstream generation
|
2023-06-19 12:40:37 -07:00 |
|
tangxifan
|
97b089ae3c
|
[test] added new testcases to validate fpga core wrapper
|
2023-06-18 21:01:37 -07:00 |
|
tangxifan
|
1ef8eed589
|
[test] update no time stamp golden outputs
|
2023-06-08 15:38:15 -07:00 |
|
tangxifan
|
31b16ba9d7
|
[test] fixed a few bugs
|
2023-05-27 12:47:57 -07:00 |
|
tangxifan
|
27b8007d1b
|
[test] rework pcf support testcase for mock wrapper
|
2023-05-27 12:45:29 -07:00 |
|
tangxifan
|
b3471f2703
|
[test] swap test name
|
2023-05-27 12:34:10 -07:00 |
|
tangxifan
|
89f184e779
|
[test] fixed a few bugs
|
2023-05-27 12:19:28 -07:00 |
|
tangxifan
|
e1feebc96d
|
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
|
2023-05-26 21:54:08 -07:00 |
|
tangxifan
|
205e9aa67b
|
[test] add a new test case
|
2023-05-26 20:55:52 -07:00 |
|
tangxifan
|
7fbe567d4c
|
[test] add more testcases
|
2023-05-25 20:24:02 -07:00 |
|
tangxifan
|
812553e13d
|
[test] adding more test cases
|
2023-05-25 20:17:23 -07:00 |
|
tangxifan
|
11832ad22c
|
[test] add a new testcase to validate mock wrapper
|
2023-05-25 20:02:10 -07:00 |
|
tangxifan
|
8d02a6e600
|
[test] now testcases are using proper arch
|
2023-05-03 21:47:21 +08:00 |
|
tangxifan
|
df771cb33a
|
[test] add a new testcase for subtile and deploy it to basic regression test
|
2023-05-03 15:41:29 +08:00 |
|
tangxifan
|
f06248a1b0
|
[test] add a new testcase to validate the ccff v2
|
2023-04-24 14:55:22 +08:00 |
|
tangxifan
|
02e964b16f
|
[test] add a new test case for ccffv2
|
2023-04-22 15:41:19 +08:00 |
|
tangxifan
|
fba0a83679
|
[test] debugging 2-clock network
|
2023-04-20 14:44:01 +08:00 |
|
tangxifan
|
02b02d18a5
|
[test] fixed a bug in clock arch
|
2023-04-20 11:35:36 +08:00 |
|
tangxifan
|
b242fd97d6
|
[test] adding new arch and testcase for 2-clock network
|
2023-04-20 11:31:49 +08:00 |
|
tangxifan
|
03cb664049
|
[test] now clock network example script supports multiple clocks
|
2023-04-20 10:56:36 +08:00 |
|
tangxifan
|
7d333b3669
|
[test] add a new test for clock network: validate full testbench is working
|
2023-04-20 10:36:08 +08:00 |
|
tangxifan
|
1f9c1fe7e1
|
[test] clean up clock network task config
|
2023-04-20 10:31:22 +08:00 |
|
tangxifan
|
fd1c4039d3
|
[test] typo
|
2023-03-02 21:37:24 -08:00 |
|
tangxifan
|
02b50e3464
|
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
|
2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
b9f7c72a96
|
[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
Ganesh Gore
|
f7c710e95e
|
renamed yosys_vpr_template fabric_netlist_gen_template
|
2023-02-11 18:33:06 -07:00 |
|
Ganesh Gore
|
b2bdfb7475
|
Strip down task
|
2023-02-11 18:32:06 -07:00 |
|
Ganesh Gore
|
b71a1014e8
|
renamed vpr_blif_template to fabric_verification_template
|
2023-02-11 18:29:21 -07:00 |
|
Ganesh Gore
|
6a48f1eb05
|
Updated demo projects
|
2023-02-11 18:24:20 -07:00 |
|
tangxifan
|
d1e951e52e
|
[test] debugging
|
2023-01-24 17:57:34 -08:00 |
|
tangxifan
|
f964c9ed67
|
[test] debug
|
2023-01-24 15:48:57 -08:00 |
|
tangxifan
|
8174f53796
|
[test] deploy new test to fpga bitstream regression
|
2023-01-24 15:42:01 -08:00 |
|
tangxifan
|
fec84d76d1
|
[arch] adding tech lib;
|
2023-01-24 15:22:34 -08:00 |
|
tangxifan
|
d60d0540da
|
[test] adding a new test case to validate the bitstream overloading for DSP blocks
|
2023-01-24 14:58:52 -08:00 |
|
tangxifan
|
f586229b97
|
[test] enable rst_on_lut benchmark
|
2023-01-18 19:45:41 -08:00 |
|
tangxifan
|
b7a66705e0
|
[test] now use yosys_vpr flow; add rst_on_lut benchmark
|
2023-01-18 19:42:50 -08:00 |
|
tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
|
2023-01-18 18:31:36 -08:00 |
|
tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
|
2023-01-18 18:17:14 -08:00 |
|
tangxifan
|
2c9593c1d4
|
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
|
2023-01-15 13:09:40 -08:00 |
|
tangxifan
|
13aed6fff5
|
[test] still commment verification out
|
2023-01-15 12:17:59 -08:00 |
|
tangxifan
|
758cc7a089
|
[test] debugging
|
2023-01-15 11:44:48 -08:00 |
|
tangxifan
|
14bb76ec87
|
[test] remove verification steps for new test but leave a todo
|
2023-01-14 23:06:54 -08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
26f71656de
|
[test] update pin constraints
|
2023-01-13 21:12:18 -08:00 |
|
tangxifan
|
93107c752a
|
[test] updating test case
|
2023-01-13 19:53:15 -08:00 |
|
tangxifan
|
1353577351
|
[test] added a new test to validate locally generated clocks
|
2023-01-13 16:45:30 -08:00 |
|
tangxifan
|
c7dc3ce7dc
|
[test] pass
|
2023-01-11 17:10:29 -08:00 |
|
tangxifan
|
f6f153ace4
|
[test] debugging
|
2023-01-11 17:06:31 -08:00 |
|
tangxifan
|
d5ebbeea9a
|
[test] adding a new test to show how to automate generation of bus group files
|
2023-01-11 16:59:54 -08:00 |
|
tangxifan
|
83d7ff56e1
|
[script] add dedicated testcase for source commands
|
2023-01-01 17:04:24 -08:00 |
|
tangxifan
|
d7a95a8ec2
|
[script] fixed some bugs
|
2022-12-30 18:30:52 -08:00 |
|
tangxifan
|
56a3e6e463
|
[test] reduce test size
|
2022-12-30 18:28:17 -08:00 |
|
tangxifan
|
ae11a4fbf2
|
[test] add a new test case
|
2022-12-30 18:25:15 -08:00 |
|
tangxifan
|
12d114bbae
|
[test] hit the bug of tileable rr_graph skip it
|
2022-11-05 10:52:04 -07:00 |
|
tangxifan
|
dc24e41c6b
|
[test] relax minW for counter128, as VPR's router degrades in routability
|
2022-11-03 19:48:13 -07:00 |
|
tangxifan
|
513f7800aa
|
[test] update golden outputs for no_cout_in_gsb testcase
|
2022-11-03 17:51:51 -07:00 |
|
tangxifan
|
a88bc2d4de
|
[test] update golden outputs for device4x4
|
2022-11-03 17:51:08 -07:00 |
|
tangxifan
|
5f74367c2e
|
[test] update golden for device1x1 no time stamp netlists
|
2022-11-03 17:48:40 -07:00 |
|
tangxifan
|
40f1f2fbc6
|
[test] update golden results for iwls
|
2022-10-21 20:28:10 -07:00 |
|
tangxifan
|
04286508c8
|
[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
|
2022-10-21 20:26:56 -07:00 |
|
tangxifan
|
00a485cbeb
|
[test] add missing file
|
2022-10-17 19:44:25 -07:00 |
|
tangxifan
|
609e096b1a
|
[test] added a new test to validate explicit port direction in pin table support
|
2022-10-17 15:25:19 -07:00 |
|
tangxifan
|
8b00bfdff9
|
[test] replace hardcoded paths in task config files with relative paths
|
2022-10-17 11:55:57 -07:00 |
|
tangxifan
|
aa78981e37
|
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
|
2022-10-17 11:18:21 -07:00 |
|
tangxifan
|
b0be27b384
|
[test] add repack design constraints files
|
2022-10-13 11:22:48 -07:00 |
|
tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
ab53f88c2b
|
[test] now use a fixed device layout for the single-mode LUT design testcase
|
2022-10-04 10:05:22 -07:00 |
|
tangxifan
|
4eaecde0b9
|
[test] add golden netlists to ensure no cout in gsb
|
2022-10-01 11:03:13 -07:00 |
|
tangxifan
|
78f30cf072
|
[test] add a new test to track the golden netlists where cout is not in GSB
|
2022-09-30 15:38:27 -07:00 |
|
tangxifan
|
0565ca7aca
|
[script] add missing files
|
2022-09-29 16:14:38 -07:00 |
|
tangxifan
|
a3e7133d63
|
Merge branch 'master' into wire_lut_test
|
2022-09-29 16:02:18 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
9bc9b61d35
|
[test] fixed a few bugs
|
2022-09-29 15:11:30 -07:00 |
|
tangxifan
|
f5e7ec4dd1
|
[test] add a new test case to validate wire lut case
|
2022-09-29 14:28:59 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
79b260f5e1
|
[arch] update missing arch
|
2022-09-21 16:52:32 -07:00 |
|
tangxifan
|
b1f8cdab3c
|
[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
|
2022-09-21 15:28:56 -07:00 |
|
tangxifan
|
b532bca9d2
|
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
|
2022-09-21 10:54:16 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
b8f1520367
|
[test] fixed a bug
|
2022-09-20 18:12:23 -07:00 |
|
tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
|
2022-09-20 18:10:52 -07:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
1b0b50b928
|
[test] update golden netlist
|
2022-09-20 16:04:05 -07:00 |
|
tangxifan
|
b630d60b7e
|
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
|
2022-09-20 14:14:18 -07:00 |
|
tangxifan
|
37c5056d6a
|
[test] now use a fixed routing channel width for quicklogic tests
|
2022-09-20 12:25:40 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
40663f956c
|
[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
|
2022-09-19 21:55:15 -07:00 |
|
tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
|
2022-09-16 10:29:19 -07:00 |
|
tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
|
2022-09-13 17:53:33 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
|
2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
|
tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
|
2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
|
2022-09-06 14:59:00 -07:00 |
|
tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
|
2022-09-06 14:04:23 -07:00 |
|
tangxifan
|
c48f750f86
|
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
|
2022-09-01 20:10:29 -07:00 |
|
tangxifan
|
51dc082bd4
|
[test] force a fixed routing chan W for no time stamp test case
|
2022-09-01 15:02:40 -07:00 |
|
tangxifan
|
d86eb04c5d
|
[test] now no timestamp test case covers gsb files
|
2022-09-01 14:03:51 -07:00 |
|
tangxifan
|
069e2b00b1
|
[test] add more test cases to validate gsb options
|
2022-08-29 22:03:06 -07:00 |
|
tangxifan
|
8b17bf1b1c
|
[test] add a new test case to validate that .act file is not required when power analysis flow is off
|
2022-08-01 18:44:47 -07:00 |
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tangxifan
|
35fe858035
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[test] fixed a few bugs
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2022-07-28 12:06:16 -07:00 |
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tangxifan
|
ca9122ddb9
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[test] fixed a bug
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2022-07-28 11:57:47 -07:00 |
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tangxifan
|
ec31e124b7
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[test] reworked test case on pcf2place
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2022-07-28 11:51:56 -07:00 |
taoli4rs
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cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
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tangxifan
|
9832722056
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[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
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tangxifan
|
86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
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2022-05-25 11:19:49 +08:00 |
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tangxifan
|
6719a9aa26
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[test] update golden netlists/testbenches etc.
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2022-05-22 13:03:01 +08:00 |
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tangxifan
|
22c4d72358
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[test] add a test case to validate negative edge-triggered ff
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2022-05-09 16:57:42 +08:00 |
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Ganesh Gore
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522982c9ba
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Adde vtr_benchmarks_template for demo
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2022-05-06 22:40:36 -06:00 |
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Ganesh Gore
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275cda081e
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[Bugfix] Typo
|
2022-05-05 08:40:21 -06:00 |
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Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
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Ganesh Gore
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21c3dbf611
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Added regression for template project
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2022-05-02 23:23:45 -06:00 |
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Ganesh Gore
|
9891e42f7a
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Added template task
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2022-05-02 11:49:16 -06:00 |
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tangxifan
|
efc25aa66e
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[Script] Fixed a bug in wrong paths
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2022-04-13 16:04:33 +08:00 |
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tangxifan
|
5beefda3bd
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[Test] Add a new test case to validate the fix_pins option
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2022-04-13 15:55:21 +08:00 |
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tangxifan
|
f8845f7d3a
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[Test] Add a test case to validate separated clock pins in global port
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2022-03-20 11:02:07 +08:00 |
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tangxifan
|
fdaf97e60d
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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tangxifan
|
a615c9d4e3
|
[Test] Rename test cases
|
2022-02-24 09:43:41 -08:00 |
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tangxifan
|
b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
|
245c7b1e45
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[Test] Add a new test case to validate config enable signal in preconfigured testbenches
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2022-02-23 16:02:00 -08:00 |
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tangxifan
|
e33ba667e4
|
[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
|
f30de1085c
|
[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
|
b4202f52b4
|
[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
|
785bb1633d
|
[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
|
7645d5332d
|
[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
|
f0ce1e79a3
|
[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
|
223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
|
5ab84e1861
|
[Test] Add a new test for bus group
|
2022-02-18 15:29:33 -08:00 |
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tangxifan
|
b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
|
2022-02-18 15:02:08 -08:00 |
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tangxifan
|
36543f7f2f
|
[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
|
tangxifan
|
8ba3d06392
|
[Test] Fixed bugs in simulation settings
|
2022-02-18 12:36:22 -08:00 |
|
tangxifan
|
a4d5172b7c
|
[Test] Fixed bugs that causes VPR failed
|
2022-02-18 12:31:29 -08:00 |
|
tangxifan
|
7176037bc4
|
[Test] Added a new test about bus group
|
2022-02-18 12:26:00 -08:00 |
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tangxifan
|
f02f3c10d4
|
[Test] Fix bugs on the remaining implicit verilog test cases
|
2022-02-15 16:49:15 -08:00 |
|
tangxifan
|
1370be0817
|
[Script] Fixing bugs
|
2022-02-15 16:44:51 -08:00 |
|
tangxifan
|
8be0868a3b
|
[Test] Update test case which uses counter benchmarks: adding pin constraints
|
2022-02-15 16:29:06 -08:00 |
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tangxifan
|
f002c79a61
|
[Test] Adapt pin constraints due to changes in pin names
|
2022-02-15 16:06:46 -08:00 |
|
tangxifan
|
b533fd17d5
|
[Test] Rework pin constraints that cause problems
|
2022-02-15 15:41:16 -08:00 |
|
tangxifan
|
9ef7ad64d8
|
[Test] Simplify paths
|
2022-02-15 15:35:21 -08:00 |
|
tangxifan
|
d0fe8d96fa
|
[Test] Update template scripts and assoicated test cases by offering more options
|
2022-02-14 16:03:48 -08:00 |
|
tangxifan
|
70363effa4
|
[Test] Add a new test to validate 8-bit counters using full testbenches
|
2022-02-14 15:57:55 -08:00 |
|
tangxifan
|
7ef808cbe4
|
[Test] Update pin constraints for different counter benchmarks
|
2022-02-14 15:28:03 -08:00 |
|
tangxifan
|
570c1b10dc
|
[Test] Add dedicated pin constraints for counter designs
|
2022-02-14 13:54:48 -08:00 |
|
tangxifan
|
85011824e2
|
[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
|
2022-02-14 13:15:55 -08:00 |
|
tangxifan
|
6630c17c23
|
[Test] Use preconfigured testbench template to run counter8 tests
|
2022-02-14 13:07:31 -08:00 |
|
tangxifan
|
da3f9ccb80
|
[Test] Truncating counter designs in each task
|
2022-02-14 12:22:19 -08:00 |
|
tangxifan
|
0268814fc6
|
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
|
2022-02-14 12:20:56 -08:00 |
|
tangxifan
|
532af96243
|
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
|
2022-02-01 13:44:47 -08:00 |
|
tangxifan
|
da8fc0f5d4
|
[Test] Add a new test case to validate ``--use_relative_path``
|
2022-01-31 13:02:19 -08:00 |
|
tangxifan
|
f8ef3df560
|
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
|
2022-01-26 11:41:48 -08:00 |
|
tangxifan
|
3b7588cd48
|
[Test] Rename test case to be consistent with the name of options
|
2022-01-26 11:25:54 -08:00 |
|
tangxifan
|
6b26ed0819
|
[Test] Add test cases on writing gsb files
|
2022-01-26 11:22:39 -08:00 |
|
tangxifan
|
23795d6474
|
[Test] Update golden netlists
|
2022-01-25 20:37:08 -08:00 |
|
tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
6e778a74ee
|
[Test] Add golden reference for files outputted without time stamp
|
2022-01-25 16:24:25 -08:00 |
|
tangxifan
|
2bee59c6ca
|
[Test] Add the testcase to validate ``--no_time_stamp``
|
2022-01-25 16:21:15 -08:00 |
|
tangxifan
|
dd803dd1de
|
[Test] Remove unused tests
|
2022-01-25 16:16:58 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
397f2e71f1
|
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
|
2022-01-19 20:43:26 +05:00 |
|
Aram Kostanyan
|
bd158311c5
|
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
|
2022-01-18 14:07:41 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
598c5e6b75
|
Test case for yosys-only flow added
|
2022-01-14 15:37:47 +05:00 |