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[test] remove verification steps for new test but leave a todo

This commit is contained in:
tangxifan 2023-01-14 23:06:54 -08:00
parent 2a0e512ac9
commit 14bb76ec87
1 changed files with 3 additions and 2 deletions
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5
openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
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@ -39,5 +39,6 @@ bench0_top = clk_divider
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=
# FIXME: Enable this once VPR can accept clock routing for specific clock signals
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=