From 14bb76ec87e098341d3565cf78cb20fe844e10e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 14 Jan 2023 23:06:54 -0800 Subject: [PATCH] [test] remove verification steps for new test but leave a todo --- .../basic_tests/k4_series/k4n4_clk_gen/config/task.conf | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf index 12ad1855b..40d11964c 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf @@ -39,5 +39,6 @@ bench0_top = clk_divider bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= +# FIXME: Enable this once VPR can accept clock routing for specific clock signals +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist=