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[test] add a new testcase for subtile and deploy it to basic regression test

This commit is contained in:
tangxifan 2023-05-03 15:41:29 +08:00
parent a3f2ae3c33
commit df771cb33a
3 changed files with 4 additions and 3 deletions
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0
openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_openfpga.xml → openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
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2
openfpga_flow/regression_test_scripts/basic_reg_test.sh
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@ -158,6 +158,8 @@ echo -e "Testing tiles with pins only on bottom and right sides";
run-task basic_tests/tile_organization/bottom_right_custom_pins $@
echo -e "Testing tiles with I/O in center grid";
run-task basic_tests/tile_organization/tileable_io $@
echo -e "Testing tiles with I/O consisting of subtiles";
run-task basic_tests/tile_organization/io_subtile $@
echo -e "Testing global port definition from tiles";
run-task basic_tests/global_tile_ports/global_tile_clock $@

5
openfpga_flow/tasks/basic_tests/tile_organization/tileable_io/config/task.conf
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@ -17,12 +17,12 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
@ -30,7 +30,6 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=