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[test] deploy new test to fpga bitstream regression

This commit is contained in:
tangxifan 2023-01-24 15:42:01 -08:00
parent 499d352cff
commit 8174f53796
2 changed files with 3 additions and 1 deletions
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2
openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
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@ -29,6 +29,8 @@ run-task fpga_bitstream/repack_wire_lut_strong $@
echo -e "Testing overloading default paths for programmable interconnect when generating bitstream";
run-task fpga_bitstream/overload_mux_default_path $@
echo -e "Testing overloading mode bits for DSP blocks when generating bitstream";
run-task fpga_bitstream/overload_dsp_mode_bit $@
echo -e "Testing outputting I/O mapping result to file";
run-task fpga_bitstream/write_io_mapping $@

2
openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf
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@ -38,7 +38,7 @@ bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D
bench_yosys_write_blif_options = -param
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mult8
bench1_top = mult16