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[test] fixed some bugs in arch

This commit is contained in:
tangxifan 2023-03-02 18:16:59 -08:00
parent 46510388be
commit b9f7c72a96
2 changed files with 4 additions and 4 deletions
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4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
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@ -18,10 +18,10 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk1clk2lvl_cc_openfpga.xml
openfpga_clock_arch_file=${TASK_DIR}/config/clk_arch_1clk_2layer.xml
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=20
openfpga_vpr_route_chan_width=24
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml

4
openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
View File

@ -170,8 +170,8 @@
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L1" freq="0.2" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L4" freq="0.8" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/>