diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
index 3b0bc7f72..d88210133 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
@@ -18,10 +18,10 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk1clk2lvl_cc_openfpga.xml
-openfpga_clock_arch_file=${TASK_DIR}/config/clk_arch_1clk_2layer.xml
+openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
-openfpga_vpr_route_chan_width=20
+openfpga_vpr_route_chan_width=24
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
index 5d5371df5..24f0704d0 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
@@ -170,8 +170,8 @@
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
- 1 1 1 1 1
- 1 1 1 1
+ 1 1
+ 1