[test] adding a new test case to validate the bitstream overloading for DSP blocks

openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v

@@ -0,0 +1,18 @@
+//-------------------------------------------------------
+//  Functionality: A 8-bit multiply circuit using macro
+//  Author:        Tarachand Pagarani
+//-------------------------------------------------------
+
+module mult16(a, b, out);
+parameter DATA_WIDTH = 16;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b;
+output [2*DATA_WIDTH - 1 : 0] out;
+
+(* keep *)
+  mult_16 #(.MODE(1'b0)) DSP (
+		.A(a),
+		.B(b),
+		.Y(out),
+	);
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v

@@ -0,0 +1,18 @@
+//-------------------------------------------------------
+//  Functionality: A 8-bit multiply circuit using macro
+//  Author:        Tarachand Pagarani
+//-------------------------------------------------------
+
+module mult8(a, b, out);
+parameter DATA_WIDTH = 8;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b;
+output [2*DATA_WIDTH - 1 : 0] out;
+
+(* keep *)
+  mult_8 #(.MODE(1'b1)) DSP (
+		.A(a),
+		.B(b),
+		.Y(out),
+	);
+
+endmodule

openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys

@@ -94,4 +94,4 @@ stat
 # Output netlists
 #########################
 opt_clean -purge
-write_blif ${OUTPUT_BLIF}
+write_blif ${YOSYS_WRITE_BLIF_OPTIONS} ${OUTPUT_BLIF}

openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/bitstream_annotation.xml

@@ -0,0 +1,4 @@
+<openfpga_bitstream_setting>
+  <pb_type name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" source="eblif" content=".param MODE" is_mode_select_bitstream="true"/>
+  <pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" source="eblif" content=".param MODE" is_mode_select_bitstream="true"/>
+</openfpga_bitstream_setting>

openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf

@@ -0,0 +1,48 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_bitstream_setting_file=${PATH:TASK_DIR}/config/bitstream_annotation.xml
+# VPR parameter
+openfpga_vpr_device_layout=3x4
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
+bench_yosys_write_blif_options = -param
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = mult8
+bench1_top = mult16
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=