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[arch] adding tech lib;

This commit is contained in:
tangxifan 2023-01-24 15:22:34 -08:00
parent 1d8c1a6803
commit fec84d76d1
4 changed files with 75 additions and 7 deletions
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4
openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml
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@ -199,8 +199,8 @@
<!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_16" physical_mode_name="mult_16x16"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
<pb_type name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" circuit_model_name="frac_mult_16x16" mode_bits="0"/>
<pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" mode_bits="1" physical_pb_type_index_factor="0">
<pb_type name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" circuit_model_name="frac_mult_16x16" mode_bits="1"/>
<pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" mode_bits="0" physical_pb_type_index_factor="0">
<port name="A" physical_mode_port="A[0:7]" physical_mode_port_rotate_offset="8"/>
<port name="B" physical_mode_port="B[0:7]" physical_mode_port_rotate_offset="8"/>
<port name="Y" physical_mode_port="Y[0:15]" physical_mode_port_rotate_offset="16"/>

27
openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v Normal file
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@ -0,0 +1,27 @@
//-----------------------------
// 8-bit multiplier
//-----------------------------
module mult_8(
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
parameter MODE = 1'b1;
assign Y = A * B;
endmodule
//-----------------------------
// 16-bit multiplier
//-----------------------------
module mult_16(
input [0:15] A,
input [0:15] B,
output [0:31] Y
);
parameter MODE = 1'b0;
assign Y = A * B;
endmodule

41
openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v Normal file
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@ -0,0 +1,41 @@
//-----------------------------
// 8-bit multiplier
//-----------------------------
module mult_8x8 (
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_8 #(.MODE(1'b1)) _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule
//-----------------------------
// 16-bit multiplier
//-----------------------------
module mult_16x16 (
input [0:15] A,
input [0:15] B,
output [0:31] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_16 #(.MODE(1'b0)) _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule

10
openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf
View File

@ -17,14 +17,14 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_bitstream_setting_file=${PATH:TASK_DIR}/config/bitstream_annotation.xml
# VPR parameter
openfpga_vpr_device_layout=3x4
openfpga_vpr_circuit_format=eblif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v
@ -32,8 +32,8 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult1
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_yosys_write_blif_options = -param
bench_read_verilog_options_common = -nolatches