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[test] debugging

This commit is contained in:
tangxifan 2023-01-24 17:57:34 -08:00
parent f964c9ed67
commit d1e951e52e
3 changed files with 19 additions and 2 deletions
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2
openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
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@ -94,4 +94,4 @@ stat
# Output netlists
#########################
opt_clean -purge
write_blif ${YOSYS_WRITE_BLIF_OPTIONS} ${OUTPUT_BLIF}
write_blif -param ${OUTPUT_BLIF}

1
openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf
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@ -35,7 +35,6 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult1
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_yosys_write_blif_options_common = -param
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

18
openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml
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@ -25,6 +25,24 @@
that describe them.
-->
<models>
<model name="mult_8">
<input_ports>
<port name="A" combinational_sink_ports="Y"/>
<port name="B" combinational_sink_ports="Y"/>
</input_ports>
<output_ports>
<port name="Y"/>
</output_ports>
</model>
<model name="mult_16">
<input_ports>
<port name="A" combinational_sink_ports="Y"/>
<port name="B" combinational_sink_ports="Y"/>
</input_ports>
<output_ports>
<port name="Y"/>
</output_ports>
</model>
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io">
<input_ports>