From d1e951e52ede4a80e313e68d9b031bfe738b98ab Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Jan 2023 17:57:34 -0800
Subject: [PATCH] [test] debugging

---
 .../misc/ys_tmpl_yosys_vpr_dsp_flow.ys         |  2 +-
 .../overload_dsp_mode_bit/config/task.conf     |  1 -
 .../k4_N4_tileable_frac_dsp16_40nm.xml         | 18 ++++++++++++++++++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
index b97bf6a18..621502032 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
@@ -94,4 +94,4 @@ stat
 # Output netlists
 #########################
 opt_clean -purge
-write_blif ${YOSYS_WRITE_BLIF_OPTIONS} ${OUTPUT_BLIF}
+write_blif -param ${OUTPUT_BLIF}
diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf
index f389d287c..b634ab62c 100644
--- a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf
@@ -35,7 +35,6 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult1
 bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v
 bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v
 bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
-bench_yosys_write_blif_options_common = -param
 bench_read_verilog_options_common = -nolatches
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml
index a6f1fa77e..ba168fc33 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml
@@ -25,6 +25,24 @@
        that describe them.
   -->
   <models>
+    <model name="mult_8">
+      <input_ports>
+        <port name="A" combinational_sink_ports="Y"/>
+        <port name="B" combinational_sink_ports="Y"/>
+      </input_ports>
+      <output_ports>
+        <port name="Y"/>
+      </output_ports>
+    </model>
+    <model name="mult_16">
+      <input_ports>
+        <port name="A" combinational_sink_ports="Y"/>
+        <port name="B" combinational_sink_ports="Y"/>
+      </input_ports>
+      <output_ports>
+        <port name="Y"/>
+      </output_ports>
+    </model>
     <!-- A virtual model for I/O to be used in the physical mode of io block -->
     <model name="io">
       <input_ports>