[test] added new test case to validate bitstream generation

openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga

@@ -24,6 +24,8 @@ lut_truth_table_fixup
 #    Note that this is turned on when bitstream generation 
 #    is the ONLY purpose of the flow!!!
 build_fabric --compress_routing --frame_view #--verbose
+# Add a fpga core between fpga top and the underlying modules
+add_fpga_core_to_fabric --instance_name fpga_core_inst --frame_view --verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation

openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh

@@ -20,6 +20,9 @@ echo -e "Testing bitstream generation for an 96x96 FPGA device";
 run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@
 run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_72x72 $@
 
+echo -e "Testing bitstream generation when fpga core wrapper is added";
+run-task fpga_bitstream/generate_bitstream/fpga_core_wrapper $@
+
 echo -e "Testing loading architecture bitstream from an external file";
 run-task fpga_bitstream/load_external_architecture_bitstream $@
 

openfpga_flow/tasks/fpga_bitstream/generate_bitstream/fpga_core_wrapper/config/task.conf

@@ -0,0 +1,33 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fpga_core_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]