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[test] still commment verification out

This commit is contained in:
tangxifan 2023-01-15 12:17:59 -08:00
parent ac8c0e243c
commit 13aed6fff5
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
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@ -40,5 +40,5 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.x
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
# FIXME: Enable this once VPR can accept clock routing for specific clock signals
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=