riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[test] debugging

This commit is contained in:
tangxifan 2023-01-11 17:06:31 -08:00
parent d5ebbeea9a
commit f6f153ace4
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/openfpga_shell_scripts/auto_bus_group_example_script.openfpga
View File

@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --verbose
# Generate a bus group file by calling an external python script
ext_exec --command "python3 --task ../../../../config/counter8_bus_group_task.yaml"
ext_exec --command "python3 ../../../../config/bus_group_gen.py --task ../../../../config/counter8_bus_group_task.yaml"
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists

2
openfpga_flow/tasks/basic_tests/bus_group/auto_gen_bus_group/config/counter8_bus_group_task.yaml
View File

@ -1,5 +1,5 @@
counter8:
source:
- counter_output_verilog.v
- ./counter_output_verilog.v
top_module: counter
bus_group_file: bus_group.xml