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[test] now clock network example script supports multiple clocks

This commit is contained in:
tangxifan 2023-04-20 10:56:36 +08:00
parent 7d333b3669
commit 03cb664049
4 changed files with 11 additions and 2 deletions
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4
openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
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@ -42,7 +42,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
@ -66,7 +66,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Finish and exit OpenFPGA
exit

3
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/dummy_pin_constraints.xml Normal file
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@ -0,0 +1,3 @@
<!-- A dummy pin constraint file, useful when no pin constraints are needed for a benchmark -->
<pin_constraints>
</pin_constraints>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/dummy_repack_constraints.xml Normal file
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@ -0,0 +1,4 @@
<!-- A dummy pin constraint file, useful when no pin constraints are needed for a benchmark -->
<repack_design_constraints>
</repack_design_constraints>

2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
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@ -22,6 +22,8 @@ openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=24
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/dummy_repack_constraints.xml
openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/dummy_pin_constraints.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml