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[test] debugging 2-clock network

This commit is contained in:
tangxifan 2023-04-20 14:44:01 +08:00
parent 02b02d18a5
commit fba0a83679
3 changed files with 6 additions and 5 deletions
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2
openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
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@ -22,7 +22,7 @@ append_clock_rr_graph
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Route clock based on clock network definition
route_clock_rr_graph
route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

5
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
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@ -1,5 +1,5 @@
<clock_networks default_segment="L1" default_switch="ipin_cblock">
<clock_network name="clk_tree_2lvl" width="1">
<clock_network name="clk_tree_2lvl" width="2">
<spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/>
@ -11,7 +11,8 @@
<spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<tap tile_pin="clb[0:0].clk[0:1]"/>
<tap tile_pin="clb[0:0].clk[0:0]"/>
<tap tile_pin="clb[0:0].clk[1:1]"/>
</taps>
</clock_network>
</clock_networks>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/pin_constraints.xml
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@ -1,4 +1,4 @@
<pin_constraints>
<set_io pin="clk0" net="clk"/>
<set_io pin="clk1" net="OPEN"/>
<set_io pin="clk[0]" net="clk"/>
<set_io pin="clk[1]" net="OPEN"/>
</pin_constraints>