Commit Graph

703 Commits

Author SHA1 Message Date
Eddie Hung dd10d2b00d Add tests for cmp2lut on LUT6 2019-07-16 12:11:59 -07:00
Eddie Hung 41243a53b3 Update test with more accurate LUT mask 2019-07-12 21:00:59 -07:00
Clifford Wolf 9546ccdbd3 Fix tests/various/async FFL test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Clifford Wolf 5138621482 Improve tests/various/async, disable failing ffl test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:21:25 +02:00
Clifford Wolf c18b23f055 Add tests/various/async.{sh,v}
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:59 +02:00
Clifford Wolf 3dd92fcd15 Improve tests/various/run-test.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:28 +02:00
Clifford Wolf f8512864cd Add tests/simple_abc9/.gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:01 +02:00
Eddie Hung de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
write_xaiger to treat unknown cell connections as keep-s
2019-07-03 09:43:00 -07:00
Clifford Wolf e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf 1f173210eb Fix tests/various/specify.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:25:05 +02:00
Clifford Wolf ba36567908 Some cleanups in "ignore specify parser"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Eddie Hung 9c556e3c02 Add test 2019-07-02 19:13:40 -07:00
Eddie Hung 8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire
Add "script -select [selection]" to allow commands to be taken from wires
2019-07-02 10:20:42 -07:00
Eddie Hung 81a717e9b7 Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00
Eddie Hung 90382a0f6d Update test too 2019-07-02 08:19:23 -07:00
David Shah d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux
Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Eddie Hung 04459cb30a Comment out invalid syntax 2019-06-30 11:48:01 -07:00
Eddie Hung fd2fb4f0f0 Merge branch 'master' into eddie/script_from_wire 2019-06-28 14:56:34 -07:00
Eddie Hung 0ec7c09756 autotest.sh to define _AUTOTB when test_autotb 2019-06-28 14:56:22 -07:00
Eddie Hung 64f6b0c747 Try command in another module 2019-06-28 13:41:32 -07:00
Eddie Hung 2c6aaef3db Add test 2019-06-28 13:32:09 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung dc677c791d Add test from #1144, and try reading without '-specify' flag 2019-06-28 10:12:48 -07:00
Clifford Wolf 74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext
tests: use optional ABCEXTERNAL when specified
2019-06-28 10:30:31 +02:00
Clifford Wolf 1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Gabriel L. Somlo 6f1c137989 tests: use optional ABCEXTERNAL when specified
Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-27 23:00:13 -04:00
Eddie Hung 9a371cfba9 Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 12:53:23 -07:00
Eddie Hung c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
tests: Check that Icarus can parse arch sim models
2019-06-27 12:31:15 -07:00
Eddie Hung 440f173aef Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:54:34 -07:00
Eddie Hung 6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung ab7c431905 Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00
Eddie Hung 18acb72c05 Add #1135 testcase 2019-06-27 11:02:52 -07:00
Eddie Hung 3910bc2ea6 Copy tests from eddie/fix1132 2019-06-27 06:01:50 -07:00
Bogdan Vukobratovic 0f32cb4e0a Merge remote-tracking branch 'upstream/master' 2019-06-27 12:11:47 +02:00
David Shah 71b046d639 tests: Check that Icarus can parse arch sim models
Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 18:46:22 +01:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung ab6e8ce0f0 Add testcase from #335, fixed by #1130 2019-06-25 08:43:58 -07:00
Clifford Wolf add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung 9dca024a30 Add tests/various/abc9.{v,ys} with SCC test 2019-06-24 21:52:53 -07:00
Eddie Hung a701a2accf Add test 2019-06-24 18:32:58 -07:00
Eddie Hung 4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung 32f637ffdb Add more tests 2019-06-21 12:31:04 -07:00
Eddie Hung ae8305ffcc Fix testcase 2019-06-21 12:13:00 -07:00
Eddie Hung 6ec8160981 Add more muxpack tests, with overlapping entries 2019-06-21 11:45:53 -07:00
Eddie Hung 63eb5cace9 Merge branch 'master' into eddie/muxpack 2019-06-21 11:17:19 -07:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf 78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118
Make genvar a signed type
2019-06-21 10:13:13 +02:00
Eddie Hung 844c42cef8 Missing a `clean` and `opt_expr -mux_bool` in test 2019-06-20 19:47:59 -07:00
Eddie Hung 75375a3fbc Add test 2019-06-20 19:47:59 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 014606affe Fix issue with part of PI being 1'bx 2019-06-20 17:38:16 -07:00
Eddie Hung c20adc5263 Add test 2019-06-20 16:07:22 -07:00
Eddie Hung d0bbf9e4d4 Extend sign extension tests 2019-06-20 12:43:59 -07:00
Eddie Hung b77322034c Remove leftover comment 2019-06-20 10:15:04 -07:00
Eddie Hung b98276fa61 Add test 2019-06-20 10:13:52 -07:00
Clifford Wolf a8c85d1b4b Update some .gitignore files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 14:27:57 +02:00
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf 6a6dd5e057 Add proper test for SV-style arrays
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:06:07 +02:00
Clifford Wolf 2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Clifford Wolf 5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Improve handling of initial/default values
2019-06-19 13:53:07 +02:00
Tobias Wölfel 8b8af10f5e Unpacked array declaration using size
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
2019-06-19 12:47:48 +02:00
Clifford Wolf c330379870 Make tests/aiger less chatty
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:20:35 +02:00
Clifford Wolf fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:12:08 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Eddie Hung 9f275c1437 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
2019-06-12 16:33:05 -07:00
Eddie Hung 2e7b3eee40 Add a couple more tests 2019-06-12 15:43:43 -07:00
Eddie Hung 2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
2019-06-12 09:05:02 -07:00
Eddie Hung 86efe9a616 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
2019-06-12 09:01:15 -07:00
Eddie Hung 45c2a5f876 Add shregmap -tech xilinx test 2019-06-12 08:34:06 -07:00
Eddie Hung a138381ac3 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-10 16:21:43 -07:00
Eddie Hung c314ca3c51 Add test 2019-06-10 16:16:26 -07:00
Eddie Hung 352c532bb2 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-10 11:02:54 -07:00
Eddie Hung 1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
Eddie Hung 1e201a9b01 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-07 16:15:19 -07:00
Eddie Hung 58f4b106f3 Merge branch 'master' into eddie/muxpack 2019-06-07 15:47:28 -07:00
Eddie Hung b959bf79c0 Add nonexcl case test, comment out two others 2019-06-07 15:35:15 -07:00
Eddie Hung 1da12c5071 Add @cliffordwolf freduce testcase 2019-06-07 12:12:11 -07:00
Eddie Hung e263bc249b Add nonexclusive test from @cliffordwolf 2019-06-07 11:54:29 -07:00
Eddie Hung 65924fd12f Test *.aag too, by using *.aig as reference 2019-06-07 11:28:05 -07:00
Eddie Hung abc40924ed Use ABC to convert from AIGER to Verilog 2019-06-07 11:06:57 -07:00
Eddie Hung ebe29b6659 Use ABC to convert AIGER to Verilog, then sat against Yosys 2019-06-07 11:05:36 -07:00
Eddie Hung 1b113a0574 Add symbols to AIGER test inputs for ABC 2019-06-07 11:05:25 -07:00
Eddie Hung 0f6e914ef6 Another muxpack test 2019-06-07 08:34:58 -07:00
Clifford Wolf 6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983
elaboration system tasks
2019-06-07 13:39:46 +02:00
Clifford Wolf f01a61f093 Rename implicit_ports.sv test to implicit_ports.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 13:12:25 +02:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf a0b57f2a6f Cleanup tux3-implicit_named_connection
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
Eddie Hung 2223ca91b0 Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:22:10 -07:00
Eddie Hung 5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
Eddie Hung eaee250a6e Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:06:59 -07:00
Eddie Hung 0a66720f6f Fix warnings 2019-06-06 14:01:42 -07:00
Eddie Hung ccdf989025 Support cascading $pmux.A with $mux.A and $mux.B 2019-06-06 13:51:22 -07:00
Eddie Hung 705388eb24 Add non exclusive test 2019-06-06 12:44:06 -07:00
Eddie Hung b8620f7b3d One more and tidy up 2019-06-06 12:03:44 -07:00
Eddie Hung 5d4eca5a29 Add a few more special case tests 2019-06-06 11:59:41 -07:00
Eddie Hung 3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
tux3 88f5977093 SystemVerilog support for implicit named port connections
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-04 10:42:42 +02:00
Eddie Hung f81a0ed92e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-03 23:07:08 -07:00
Maciej Kurc 5739cf5265 Added tests for attributes
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-03 09:25:20 +02:00
Eddie Hung 25befbf542 Rename to #23 2019-05-29 15:26:33 -07:00
Eddie Hung aa2380c17a Add abc_test024 2019-05-29 15:24:38 -07:00
Eddie Hung 92197326b8 Add abc9_test022 2019-05-28 12:43:07 -07:00
Clifford Wolf 349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047
Do not use shiftmul peepopt pattern when mul result is truncated
2019-05-28 19:02:26 +02:00
Eddie Hung 5f39c262c2 From master 2019-05-28 09:38:58 -07:00
Eddie Hung ba9513b325 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-28 09:30:53 -07:00
Clifford Wolf cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 17:17:56 +02:00
Clifford Wolf e3ebac44df Add actual wandwor test that is part of "make test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:42:50 +02:00
Bogdan Vukobratovic 9a468f81c4 Optimizing DFFs whose initial value prevents their value from changing
This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
2019-05-28 08:48:21 +02:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel f68b658b4b reformat wand/wor test 2019-05-27 18:45:54 +02:00
Stefan Biereigel c5fe04acfd remove port direction workaround from test case 2019-05-27 18:10:39 +02:00
Eddie Hung f3e86e06e6 Fix init 2019-05-24 18:43:26 -07:00
Eddie Hung e1cb1bb948 Fix typos 2019-05-24 18:34:27 -07:00
Eddie Hung d15da4bc11 Add more tests 2019-05-24 18:33:18 -07:00
Eddie Hung 4bd9465ed3 Call proc 2019-05-24 18:32:02 -07:00
Eddie Hung f0c6b73b72 Fix duplicate driver 2019-05-24 17:44:57 -07:00
Eddie Hung 68359bcd6f Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux 2019-05-23 13:37:53 -07:00
Eddie Hung 47f9ea142f Add opt_rmdff tests 2019-05-23 11:26:38 -07:00
Stefan Biereigel c2caf85f7c add simple test case for wand/wor 2019-05-23 13:57:27 +02:00
Eddie Hung fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Maciej Kurc 1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00
Clifford Wolf b7ec698d40 Add test case from #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:58:04 +02:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf 1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf 7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf d97c644bc1 Add tests/various/chparam.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 16:03:15 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf 8c6e94d57c Improve tests/various/specify.ys
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:26:15 +02:00
Eddie Hung 554c58715a More testing 2019-05-03 15:54:25 -07:00
Eddie Hung bfb8b3018b Fix spacing 2019-05-03 15:42:02 -07:00
Eddie Hung 09841c2ac1 Add quick-and-dirty specify tests 2019-05-03 15:35:26 -07:00
Eddie Hung 1e5f072c05 iverilog with simcells.v as well 2019-05-03 14:03:51 -07:00
Clifford Wolf 373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Clifford Wolf 71ede7cb05
Merge pull request #976 from YosysHQ/clifford/fix974
Fix width detection of memory access with bit slice
2019-05-03 15:29:44 +02:00
Clifford Wolf d2aa123226 Fix typo in tests/svinterfaces/runone.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 14:40:51 +02:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Eddie Hung 8829cba901 Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux 2019-05-02 11:25:34 -07:00
Eddie Hung 5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
Jakob Wenzel 98ffe5fb00 fail svinterfaces testcases on yosys error exit 2019-05-02 09:52:30 +02:00
Jim Lawson 38f5424f92 Fix #938 - Crash occurs in case when use write_firrtl command
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
2019-05-01 13:16:01 -07:00
Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf e5cb9435a0 Add additional test cases for for-loops
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:32:07 +02:00
Clifford Wolf b515fd2d25 Add peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00
Eddie Hung 0f1ba94924 Remove split_shiftx tests 2019-04-26 19:45:47 -07:00
Eddie Hung 880652283c Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux 2019-04-25 18:52:20 -07:00
Eddie Hung 0eb7150a57 Add test 2019-04-25 18:08:05 -07:00
Eddie Hung eec314e262 Remove topo sort no-loop assertion, with test 2019-04-24 21:06:53 -07:00
Eddie Hung bfd71e0990 Fix abc9 with (* keep *) wires 2019-04-23 16:11:14 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf a80e74dc20 Updaye pmux2shiftx test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 16:17:43 +02:00
Clifford Wolf b40af877f3
Merge pull request #909 from zachjs/master
support repeat loops with constant repeat counts outside of constant functions
2019-04-22 08:51:34 +02:00
Clifford Wolf a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
Add pmux2shiftx command
2019-04-22 08:39:37 +02:00
Eddie Hung 42a6e0b0b9 Merge remote-tracking branch 'origin/clifford/libwb' into xaig 2019-04-21 14:49:18 -07:00
Clifford Wolf d38f0c1a96 Fix tests
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-21 11:40:20 +02:00
Eddie Hung caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Clifford Wolf b3a3e08e38 Improve "pmux2shiftx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 02:03:44 +02:00
Clifford Wolf 37728520a6 Improvements in "pmux2shiftx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:15:48 +02:00
Eddie Hung 59c993e437 Select to find union of both sets on stack 2019-04-19 15:47:53 -07:00
Clifford Wolf 0070184ea9 Improvements in pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf 4c831d72ef Add test for pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf ea2a21445e Add tests/aiger/.gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-19 14:04:12 +02:00
Eddie Hung 0c8a839f13 Re-enable partsel.v test 2019-04-16 13:10:35 -07:00
Eddie Hung 0391499e46 Merge remote-tracking branch 'origin/master' into xaig 2019-04-15 21:56:45 -07:00
Eddie Hung b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
Eddie Hung f77da46a87 Merge remote-tracking branch 'origin/master' into xaig 2019-04-12 12:21:48 -07:00
Eddie Hung 7685469ee2 Add default entry to testcase 2019-04-11 15:03:40 -07:00
Zachary Snow 5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Eddie Hung bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Eddie Hung ad602438b8 Add retime test 2019-04-05 16:28:46 -07:00
Niels Moseley ee130f67cd Liberty file parser now accepts superfluous ; 2019-03-27 15:16:19 +01:00
Niels Moseley 487cb45b87 Liberty file parser now accepts superfluous ; 2019-03-27 15:15:53 +01:00
Clifford Wolf c863796e9f Fix "verific -extnets" for more complex situations
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:17:46 +01:00
Niels Moseley 3b3b77291a Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. 2019-03-24 22:54:18 +01:00
Eddie Hung 02e8dc7ad2 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-03-19 08:52:31 -07:00
Zachary Snow a5f4b83637 fix local name resolution in prefix constructs 2019-03-18 20:43:20 -04:00
Clifford Wolf a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 22:44:37 -08:00
Jim Lawson d6c4dfb902 Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".
2019-03-04 13:37:23 -08:00
Clifford Wolf b84febafd7 Hotfix for "make test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:26:54 -08:00
Clifford Wolf 241901461a Add "write_verilog -siminit"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 15:03:03 -08:00
Eddie Hung f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Eddie Hung dfb23a79dd Uncomment out more tests 2019-02-26 12:18:48 -08:00
Eddie Hung 66b5f5166b Enable two inout tests 2019-02-26 11:39:17 -08:00
Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
Eddie Hung 65c8ccf7b5 Add broken testcases 2019-02-25 15:06:23 -08:00
Clifford Wolf c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
Define basic_cell_type() function and use it to derive the cell type …
2019-02-24 11:39:13 -08:00
Clifford Wolf da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
2019-02-24 11:29:14 -08:00
Clifford Wolf 1816fe06af Fix handling of defparam for when default_nettype is none
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
Jim Lawson 71bcc4c644 Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Keith Rothman 25680f6a07 Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-22 10:30:42 -08:00
Eddie Hung ca870688c3 Revert "tests/simple to also do LUT synth"
This reverts commit 5994382a20.
2019-02-21 13:15:45 -08:00
Eddie Hung a8803a1519 Merge remote-tracking branch 'origin/master' into xaig 2019-02-21 11:23:00 -08:00
Eddie Hung 5994382a20 tests/simple to also do LUT synth 2019-02-21 11:16:57 -08:00
Eddie Hung 107da3becf Working simple_abc9 tests 2019-02-21 11:16:25 -08:00
Eddie Hung c6fd057eda Add abc9.v testcase to simple_abc9 2019-02-21 10:37:45 -08:00
Eddie Hung be061810d7 Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig 2019-02-21 09:31:17 -08:00
Eddie Hung 8e789da74c Revert "Add -B option to autotest.sh to append to backend_opts"
This reverts commit 281f2aadca.
2019-02-21 09:22:29 -08:00
Eddie Hung 869343b040 simple_abc9 tests to now preserve memories 2019-02-20 16:19:01 -08:00
Eddie Hung 4035ec8933 Remove simple_defparam tests 2019-02-20 15:45:45 -08:00
Eddie Hung 43d5471570 Move tests/techmap/abc9 to simple_abc9 2019-02-20 15:34:59 -08:00
Eddie Hung 945bbcc298 Add tests/simple_abc9 2019-02-20 15:31:35 -08:00
Eddie Hung ef1a1402bc Add a quick abc9 test 2019-02-19 15:25:03 -08:00
Jim Lawson 5c4a72c43e Fix normal (non-array) hierarchy -auto-top.
Add simple test.
2019-02-19 14:35:15 -08:00
Eddie Hung f9af902532 Merge branch 'master' into xaig 2019-02-19 14:20:04 -08:00
Eddie Hung 430a7548bc One more merge conflict 2019-02-17 11:50:55 -08:00
Eddie Hung 17cd5f759f Merge https://github.com/YosysHQ/yosys into dff_init 2019-02-17 11:49:06 -08:00
Eddie Hung 03a533d102 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-02-17 11:44:01 -08:00
Jim Lawson 34153adef4 Append (instead of over-writing) EXTRA_FLAGS 2019-02-15 11:56:51 -08:00
Jim Lawson fc1c9aa11f Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
2019-02-15 11:14:17 -08:00
Eddie Hung 587872236e Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
Eddie Hung 4e6c5e4672 Add binary AIGs converted from AAG 2019-02-08 11:41:25 -08:00
Eddie Hung 4167b15de5 Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig 2019-02-06 14:31:11 -08:00
Eddie Hung 3f87cf86cc Revert most of autotest.sh; for non *.v use Yosys to translate 2019-02-06 14:30:19 -08:00
Eddie Hung 115883f467 Add tests for simple cases using defparam 2019-02-06 14:15:17 -08:00
Eddie Hung 281f2aadca Add -B option to autotest.sh to append to backend_opts 2019-02-06 14:14:55 -08:00
Eddie Hung 03cf1532a7 Extend testcase 2019-02-06 14:02:11 -08:00
Eddie Hung a9674bd2ec Add testcase 2019-02-06 12:49:30 -08:00
Eddie Hung fdd55d064b Rename ASCII tests 2019-02-06 12:20:36 -08:00
Eddie Hung 3f0bb441f8 Add tests 2019-02-04 16:46:24 -08:00
Clifford Wolf 9666cca9dd Remove asicworld tests for (unsupported) switch-level modelling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-27 09:17:02 +01:00
Clifford Wolf 0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp
opt_expr: refactor and improve simplification of comparisons
2019-01-02 17:34:04 +01:00
whitequark bf8db55ef3 opt_expr: improve simplification of comparisons with large constants.
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
whitequark a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark 4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark 9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark 8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1.
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
2019-01-02 02:45:49 +00:00
whitequark 42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Larry Doolittle 99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Clifford Wolf 2a681909df
Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
whitequark 7ff5a9db2d equiv_opt: pass -D EQUIV when techmapping.
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
whitequark c38ea9ae65 equiv_opt: new command, for verifying optimization passes. 2018-12-07 17:20:34 +00:00
whitequark 7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
Clifford Wolf 7d1088afc4 Add missing .gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:37 +01:00
whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
whitequark 45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark 9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf 6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error
More meaningful SystemVerilog/Verilog parser error messages
2018-10-25 13:18:59 +02:00
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
Udi Finkelstein 106af19b69 Fixed typo (sikp -> skip) 2018-06-05 22:41:27 +03:00