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Code Issues Projects Releases Wiki Activity

iverilog with simcells.v as well

This commit is contained in:
Eddie Hung 2019-05-03 14:03:51 -07:00
parent 373b236108
commit 1e5f072c05
1 changed files with 2 additions and 1 deletions
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3
tests/tools/autotest.sh
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@ -147,7 +147,8 @@ do
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
"$toolsdir"/../../techlibs/common/simlib.v
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0