Add quick-and-dirty specify tests

This commit is contained in:
Eddie Hung 2019-05-03 15:35:26 -07:00
parent d9c4644e88
commit 09841c2ac1
2 changed files with 53 additions and 0 deletions

28
tests/various/specify.v Normal file
View File

@ -0,0 +1,28 @@
module test (
input EN, CLK,
input [3:0] D,
output reg [3:0] Q
);
always @(posedge CLK)
if (EN) Q <= D;
specify
if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
endspecify
endmodule
module test2 (
input A, B,
output Q
);
xor (Q, A, B);
specify
//specparam T_rise = 1;
//specparam T_fall = 2;
`define T_rise 1
`define T_fall 2
(A => Q) = (`T_rise,`T_fall);
endspecify
endmodule

25
tests/various/specify.ys Normal file
View File

@ -0,0 +1,25 @@
read_verilog -specify specify.v
prep
cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
cd test2
select t:$specify2 -assert-count 1
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
write_verilog specify.out
design -stash gold
read_verilog -specify specify.out
cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
cd test2
select t:$specify2 -assert-count 1
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
design -stash gate
# TODO: How to check $specify and $specrule-s are equivalent?