mirror of https://github.com/YosysHQ/yosys.git
Fix tests
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -7,7 +7,7 @@ use_modelsim=false
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verbose=false
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keeprunning=false
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makejmode=false
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frontend="verilog"
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frontend="verilog -noblackbox"
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backend_opts="-noattr -noexpr -siminit"
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autotb_opts=""
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include_opts=""
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@ -137,7 +137,7 @@ do
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egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
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else
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"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
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frontend="verilog"
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frontend="verilog -noblackbox"
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fi
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if [ ! -f ../${bn}_tb.v ]; then
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@ -53,6 +53,7 @@ echo -n " no explicit top - "
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module noTop(a, y);
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input a;
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output [31:0] y;
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assign y = a;
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endmodule
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EOV
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hierarchy -auto-top
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