Fix tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-21 11:40:20 +02:00
parent 5b7fea5245
commit d38f0c1a96
2 changed files with 3 additions and 2 deletions

View File

@ -7,7 +7,7 @@ use_modelsim=false
verbose=false
keeprunning=false
makejmode=false
frontend="verilog"
frontend="verilog -noblackbox"
backend_opts="-noattr -noexpr -siminit"
autotb_opts=""
include_opts=""
@ -137,7 +137,7 @@ do
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
else
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
frontend="verilog"
frontend="verilog -noblackbox"
fi
if [ ! -f ../${bn}_tb.v ]; then

View File

@ -53,6 +53,7 @@ echo -n " no explicit top - "
module noTop(a, y);
input a;
output [31:0] y;
assign y = a;
endmodule
EOV
hierarchy -auto-top