mirror of https://github.com/YosysHQ/yosys.git
support repeat loops with constant repeat counts outside of constant functions
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@ -1030,7 +1030,26 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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log_file_error(filename, linenum, "While loops are only allowed in constant functions!\n");
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if (type == AST_REPEAT)
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log_file_error(filename, linenum, "Repeat loops are only allowed in constant functions!\n");
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{
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AstNode *count = children[0];
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AstNode *body = children[1];
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// eval count expression
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while (count->simplify(true, false, false, stage, 32, true, false)) { }
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if (count->type != AST_CONSTANT)
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log_file_error(filename, linenum, "Repeat loops outside must have constant repeat counts!\n");
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// convert to a block with the body repeated n times
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type = AST_BLOCK;
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children.clear();
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for (int i = 0; i < count->bitsAsConst().as_int(); i++)
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children.insert(children.begin(), body->clone());
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delete count;
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delete body;
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did_something = true;
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}
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// unroll for loops and generate-for blocks
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if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0)
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@ -0,0 +1,38 @@
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// coverage for repeat loops outside of constant functions
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module counter1(clk, rst, ping);
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input clk, rst;
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output ping;
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reg [31:0] count;
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always @(posedge clk) begin
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if (rst)
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count <= 0;
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else
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count <= count + 1;
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end
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assign ping = &count;
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endmodule
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module counter2(clk, rst, ping);
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input clk, rst;
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output ping;
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reg [31:0] count;
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integer i;
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reg carry;
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always @(posedge clk) begin
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carry = 1;
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i = 0;
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repeat (32) begin
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count[i] <= !rst & (count[i] ^ carry);
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carry = count[i] & carry;
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i = i+1;
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end
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end
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assign ping = &count;
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endmodule
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@ -0,0 +1,10 @@
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read_verilog counters-repeat.v
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proc; opt
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expose -shared counter1 counter2
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miter -equiv -make_assert -make_outputs counter1 counter2 miter
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cd miter; flatten; opt
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sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs
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