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Merge pull request #907 from YosysHQ/clifford/fix906 

Build Verilog parser with -DYYMAXDEPTH=100000
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Clifford Wolf 2019-03-30 00:09:42 +01:00 committed by GitHub
parent 32bd0f22ec 584d2030bf
commit 22035c20ff
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frontends/verilog/Makefile.inc
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@ -14,6 +14,8 @@ frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
$(Q) mkdir -p $(dir $@)
$(P) flex -o frontends/verilog/verilog_lexer.cc $<
frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=100000
OBJS += frontends/verilog/verilog_parser.tab.o
OBJS += frontends/verilog/verilog_lexer.o
OBJS += frontends/verilog/preproc.o