mirror of https://github.com/YosysHQ/yosys.git
Add "write_verilog -siminit"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -33,7 +33,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal;
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
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int auto_name_counter, auto_name_offset, auto_name_digits;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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@ -1310,7 +1310,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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}
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}
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if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
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if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
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std::stringstream ss;
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dump_reg_init(ss, cell->getPort("\\Q"));
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if (!ss.str().empty()) {
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@ -1607,6 +1607,10 @@ struct VerilogBackend : public Backend {
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log(" without this option all internal cells are converted to Verilog\n");
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log(" expressions.\n");
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log("\n");
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log(" -siminit\n");
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log(" add initial statements with hierarchical refs to initialize FFs when\n");
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log(" in -noexpr mode.\n");
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log("\n");
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log(" -nodec\n");
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log(" 32-bit constant values are by default dumped as decimal numbers,\n");
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log(" not bit pattern. This option deactivates this feature and instead\n");
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@ -1663,6 +1667,7 @@ struct VerilogBackend : public Backend {
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nostr = false;
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defparam = false;
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decimal = false;
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siminit = false;
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auto_prefix = "";
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bool blackboxes = false;
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@ -1739,6 +1744,10 @@ struct VerilogBackend : public Backend {
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decimal = true;
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continue;
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}
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if (arg == "-siminit") {
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siminit = true;
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continue;
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}
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if (arg == "-blackboxes") {
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blackboxes = true;
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continue;
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@ -8,7 +8,7 @@ verbose=false
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keeprunning=false
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makejmode=false
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frontend="verilog"
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backend_opts="-noattr -noexpr"
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backend_opts="-noattr -noexpr -siminit"
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autotb_opts=""
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include_opts=""
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xinclude_opts=""
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