SergeyDegtyar
b835ec37cb
Add temp directory
2019-08-21 07:53:34 +03:00
Eddie Hung
fce8dc7db2
Add test
2019-08-20 20:05:16 -07:00
SergeyDegtyar
71dd412ac5
Fix tests; Remove simulation;
...
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
2019-08-20 15:52:25 +03:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen
2019-08-20 11:39:23 +02:00
Clifford Wolf
6ffb910d12
Add test case for real parameters
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-20 11:38:21 +02:00
SergeyDegtyar
153ec0541c
Add new tests for ice40 architecture
2019-08-20 07:50:05 +03:00
whitequark
4a942ba7b9
proc_clean: fix order of switch insertion.
...
Fixes #1268 .
2019-08-19 16:44:23 +00:00
Clifford Wolf
21699e5840
Add *.sv to tests/simple_abc9/.gitignore
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-19 13:04:57 +02:00
Clifford Wolf
1e3dd0a2da
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
2019-08-19 13:04:06 +02:00
Eddie Hung
e34f2de55d
Merge remote-tracking branch 'origin/master' into clifford/testfast
2019-08-18 21:29:15 -07:00
Eddie Hung
f5170a7eda
Removal of more `stat` calls from tests
2019-08-18 21:28:45 -07:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Clifford Wolf
9e940f1276
Speed up "make test" and related cleanups
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:37:07 +02:00
Clifford Wolf
f20be90436
Add test for pmtest_test "reduce" demo pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:05:10 +02:00
Eddie Hung
51d28645da
Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share
2019-08-16 13:40:29 -07:00
Clifford Wolf
40c40d9f5d
Do not use Verific in tests/various/write_gzip.ys
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:22:46 +02:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
...
This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
Eddie Hung
88d5185596
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
2019-08-11 21:13:40 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Eddie Hung
0adf81cb91
Add $alu tests
2019-08-09 12:13:17 -07:00
Eddie Hung
8350dfb809
Add alumacc versions of opt_expr tests
2019-08-09 10:30:53 -07:00
Eddie Hung
9300111601
Add new $alu test, remove wreduce
2019-08-09 10:22:06 -07:00
Eddie Hung
313c9ec8df
Cleanup some more
2019-08-09 10:13:49 -07:00
Eddie Hung
d9c1664462
Simplify opt_expr tests using equiv_opt
2019-08-09 10:08:17 -07:00
Eddie Hung
8bf45f34c4
Remove dump call
2019-08-07 21:36:02 -07:00
Eddie Hung
2b6cdfb39f
Move tests/various/opt* into tests/opt/
2019-08-07 21:35:48 -07:00
Eddie Hung
d5e8c0e6d3
Remove ice40_unlut call, simply do equiv_opt on synth_ice40
2019-08-07 21:33:56 -07:00
Eddie Hung
35bf509603
Add testcase from removed opt_ff.{v,ys}
2019-08-07 21:31:32 -07:00
Eddie Hung
4545bf482f
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
2019-08-07 16:48:38 -07:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
...
wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
...
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
Bogdan Vukobratovic
067b44938c
Fix wrong results when opt_share called before opt_clean
2019-08-07 09:30:58 +02:00
Eddie Hung
2d1b517b01
Add signed opt_expr tests
2019-08-06 15:40:30 -07:00
Eddie Hung
769c750c22
Add signed test
2019-08-06 15:38:43 -07:00
Eddie Hung
51b39219cd
Move LSB tests from wreduce to opt_expr
2019-08-06 15:24:49 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
David Shah
3a3da678ad
Add test for writing gzip-compressed files
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 17:43:04 +01:00
Bogdan Vukobratovic
6a796accc0
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic
d8be5ce6ba
Tabs to spaces in opt_share examples
2019-08-03 12:35:46 +02:00
Bogdan Vukobratovic
280c4e7794
Fix spacing in opt_share tests, change wording in opt_share help
2019-08-03 12:28:46 +02:00
Jim Lawson
3b8c917025
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
...
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
...
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
David Shah
933db0410e
Add support for reading gzip'd input files
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
Eddie Hung
c926eeb43a
Add another test
2019-07-19 14:02:46 -07:00
Eddie Hung
5bd088a686
Add one more test with trimming Y_WIDTH of $sub
2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df
Be more explicit
2019-07-19 12:53:18 -07:00
Eddie Hung
4e9b1d36fa
Add tests for sub too
2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2
Add test
2019-07-19 12:43:02 -07:00
Eddie Hung
8a2a2cd035
Forgot to commit
2019-07-16 12:44:26 -07:00
Eddie Hung
dd10d2b00d
Add tests for cmp2lut on LUT6
2019-07-16 12:11:59 -07:00
Eddie Hung
41243a53b3
Update test with more accurate LUT mask
2019-07-12 21:00:59 -07:00
Clifford Wolf
9546ccdbd3
Fix tests/various/async FFL test
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Clifford Wolf
5138621482
Improve tests/various/async, disable failing ffl test
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:21:25 +02:00
Clifford Wolf
c18b23f055
Add tests/various/async.{sh,v}
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:59 +02:00
Clifford Wolf
3dd92fcd15
Improve tests/various/run-test.sh
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:28 +02:00
Clifford Wolf
f8512864cd
Add tests/simple_abc9/.gitignore
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:01 +02:00
Eddie Hung
de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
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write_xaiger to treat unknown cell connections as keep-s
2019-07-03 09:43:00 -07:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
...
Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf
1f173210eb
Fix tests/various/specify.v
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:25:05 +02:00
Clifford Wolf
ba36567908
Some cleanups in "ignore specify parser"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Eddie Hung
9c556e3c02
Add test
2019-07-02 19:13:40 -07:00
Eddie Hung
8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire
...
Add "script -select [selection]" to allow commands to be taken from wires
2019-07-02 10:20:42 -07:00
Eddie Hung
81a717e9b7
Update test for Pass::call_on_module()
2019-07-02 08:22:31 -07:00
Eddie Hung
90382a0f6d
Update test too
2019-07-02 08:19:23 -07:00
David Shah
d45936fe5f
memory_dff: Fix checking of feedback mux input when more than one mux
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Eddie Hung
04459cb30a
Comment out invalid syntax
2019-06-30 11:48:01 -07:00
Eddie Hung
fd2fb4f0f0
Merge branch 'master' into eddie/script_from_wire
2019-06-28 14:56:34 -07:00
Eddie Hung
0ec7c09756
autotest.sh to define _AUTOTB when test_autotb
2019-06-28 14:56:22 -07:00
Eddie Hung
64f6b0c747
Try command in another module
2019-06-28 13:41:32 -07:00
Eddie Hung
2c6aaef3db
Add test
2019-06-28 13:32:09 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
...
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung
dc677c791d
Add test from #1144 , and try reading without '-specify' flag
2019-06-28 10:12:48 -07:00
Clifford Wolf
74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext
...
tests: use optional ABCEXTERNAL when specified
2019-06-28 10:30:31 +02:00
Clifford Wolf
1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
...
Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Gabriel L. Somlo
6f1c137989
tests: use optional ABCEXTERNAL when specified
...
Commits 65924fd1
, abc40924
, and ebe29b66
hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-27 23:00:13 -04:00
Eddie Hung
9a371cfba9
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 12:53:23 -07:00
Eddie Hung
c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
...
tests: Check that Icarus can parse arch sim models
2019-06-27 12:31:15 -07:00
Eddie Hung
440f173aef
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 11:54:34 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
...
Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
ab7c431905
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
Eddie Hung
18acb72c05
Add #1135 testcase
2019-06-27 11:02:52 -07:00
Eddie Hung
3910bc2ea6
Copy tests from eddie/fix1132
2019-06-27 06:01:50 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
David Shah
71b046d639
tests: Check that Icarus can parse arch sim models
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 18:46:22 +01:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Eddie Hung
ab6e8ce0f0
Add testcase from #335 , fixed by #1130
2019-06-25 08:43:58 -07:00
Clifford Wolf
add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
...
memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung
9dca024a30
Add tests/various/abc9.{v,ys} with SCC test
2019-06-24 21:52:53 -07:00
Eddie Hung
a701a2accf
Add test
2019-06-24 18:32:58 -07:00
Eddie Hung
4ddc0354c1
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-22 14:40:55 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
...
Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung
32f637ffdb
Add more tests
2019-06-21 12:31:04 -07:00
Eddie Hung
ae8305ffcc
Fix testcase
2019-06-21 12:13:00 -07:00
Eddie Hung
6ec8160981
Add more muxpack tests, with overlapping entries
2019-06-21 11:45:53 -07:00
Eddie Hung
63eb5cace9
Merge branch 'master' into eddie/muxpack
2019-06-21 11:17:19 -07:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
...
Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118
...
Make genvar a signed type
2019-06-21 10:13:13 +02:00
Eddie Hung
844c42cef8
Missing a `clean` and `opt_expr -mux_bool` in test
2019-06-20 19:47:59 -07:00
Eddie Hung
75375a3fbc
Add test
2019-06-20 19:47:59 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
014606affe
Fix issue with part of PI being 1'bx
2019-06-20 17:38:16 -07:00
Eddie Hung
c20adc5263
Add test
2019-06-20 16:07:22 -07:00
Eddie Hung
d0bbf9e4d4
Extend sign extension tests
2019-06-20 12:43:59 -07:00
Eddie Hung
b77322034c
Remove leftover comment
2019-06-20 10:15:04 -07:00
Eddie Hung
b98276fa61
Add test
2019-06-20 10:13:52 -07:00
Clifford Wolf
a8c85d1b4b
Update some .gitignore files
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 14:27:57 +02:00
Clifford Wolf
2454ad99bf
Refactor "opt_rmdff -sat"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
6a6dd5e057
Add proper test for SV-style arrays
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:06:07 +02:00
Clifford Wolf
2428fb7dc2
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays
2019-06-20 12:03:00 +02:00
Clifford Wolf
5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
...
Improve handling of initial/default values
2019-06-19 13:53:07 +02:00
Tobias Wölfel
8b8af10f5e
Unpacked array declaration using size
...
Allows fixed-sized array dimension specified by a single number.
This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560 .
But is split out of the original work.
2019-06-19 12:47:48 +02:00
Clifford Wolf
c330379870
Make tests/aiger less chatty
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:20:35 +02:00
Clifford Wolf
fa5fc3f6af
Add defvalue test, minor autotest fixes for .sv files
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:12:08 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Eddie Hung
9f275c1437
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
...
This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 16:33:05 -07:00
Eddie Hung
2e7b3eee40
Add a couple more tests
2019-06-12 15:43:43 -07:00
Eddie Hung
2cbcd6224c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
...
This reverts commit a138381ac3
, reversing
changes made to b77c5da769
.
2019-06-12 09:05:02 -07:00
Eddie Hung
86efe9a616
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
...
This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 09:01:15 -07:00
Eddie Hung
45c2a5f876
Add shregmap -tech xilinx test
2019-06-12 08:34:06 -07:00
Eddie Hung
a138381ac3
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-10 16:21:43 -07:00
Eddie Hung
c314ca3c51
Add test
2019-06-10 16:16:26 -07:00
Eddie Hung
352c532bb2
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-10 11:02:54 -07:00
Eddie Hung
1dd7e23a20
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-10 10:28:40 -07:00
Eddie Hung
a91ea6612a
Add some more comments
2019-06-10 10:27:55 -07:00
Eddie Hung
1e201a9b01
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-07 16:15:19 -07:00
Eddie Hung
58f4b106f3
Merge branch 'master' into eddie/muxpack
2019-06-07 15:47:28 -07:00
Eddie Hung
b959bf79c0
Add nonexcl case test, comment out two others
2019-06-07 15:35:15 -07:00
Eddie Hung
1da12c5071
Add @cliffordwolf freduce testcase
2019-06-07 12:12:11 -07:00
Eddie Hung
e263bc249b
Add nonexclusive test from @cliffordwolf
2019-06-07 11:54:29 -07:00
Eddie Hung
65924fd12f
Test *.aag too, by using *.aig as reference
2019-06-07 11:28:05 -07:00
Eddie Hung
abc40924ed
Use ABC to convert from AIGER to Verilog
2019-06-07 11:06:57 -07:00
Eddie Hung
ebe29b6659
Use ABC to convert AIGER to Verilog, then sat against Yosys
2019-06-07 11:05:36 -07:00
Eddie Hung
1b113a0574
Add symbols to AIGER test inputs for ABC
2019-06-07 11:05:25 -07:00
Eddie Hung
0f6e914ef6
Another muxpack test
2019-06-07 08:34:58 -07:00
Clifford Wolf
6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983
...
elaboration system tasks
2019-06-07 13:39:46 +02:00
Clifford Wolf
f01a61f093
Rename implicit_ports.sv test to implicit_ports.v
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 13:12:25 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f
Cleanup tux3-implicit_named_connection
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
2019-06-07 11:41:54 +02:00
Eddie Hung
2223ca91b0
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:22:10 -07:00
Eddie Hung
5c277c6325
Fix and test for balanced case
2019-06-06 14:21:34 -07:00
Eddie Hung
eaee250a6e
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:06:59 -07:00
Eddie Hung
0a66720f6f
Fix warnings
2019-06-06 14:01:42 -07:00
Eddie Hung
ccdf989025
Support cascading $pmux.A with $mux.A and $mux.B
2019-06-06 13:51:22 -07:00
Eddie Hung
705388eb24
Add non exclusive test
2019-06-06 12:44:06 -07:00
Eddie Hung
b8620f7b3d
One more and tidy up
2019-06-06 12:03:44 -07:00
Eddie Hung
5d4eca5a29
Add a few more special case tests
2019-06-06 11:59:41 -07:00
Eddie Hung
3e76e3a6fa
Add tests, fix for !=
2019-06-06 11:54:38 -07:00
tux3
88f5977093
SystemVerilog support for implicit named port connections
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This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Maciej Kurc
b79bd5b3ca
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-04 10:42:42 +02:00
Eddie Hung
f81a0ed92e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-03 23:07:08 -07:00
Maciej Kurc
5739cf5265
Added tests for attributes
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-03 09:25:20 +02:00
Eddie Hung
25befbf542
Rename to #23
2019-05-29 15:26:33 -07:00
Eddie Hung
aa2380c17a
Add abc_test024
2019-05-29 15:24:38 -07:00
Eddie Hung
92197326b8
Add abc9_test022
2019-05-28 12:43:07 -07:00
Clifford Wolf
349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047
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Do not use shiftmul peepopt pattern when mul result is truncated
2019-05-28 19:02:26 +02:00
Eddie Hung
5f39c262c2
From master
2019-05-28 09:38:58 -07:00
Eddie Hung
ba9513b325
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-28 09:30:53 -07:00
Clifford Wolf
cb285e4b87
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 17:17:56 +02:00
Clifford Wolf
e3ebac44df
Add actual wandwor test that is part of "make test"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:42:50 +02:00
Bogdan Vukobratovic
9a468f81c4
Optimizing DFFs whose initial value prevents their value from changing
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This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
2019-05-28 08:48:21 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
f68b658b4b
reformat wand/wor test
2019-05-27 18:45:54 +02:00
Stefan Biereigel
c5fe04acfd
remove port direction workaround from test case
2019-05-27 18:10:39 +02:00
Eddie Hung
f3e86e06e6
Fix init
2019-05-24 18:43:26 -07:00
Eddie Hung
e1cb1bb948
Fix typos
2019-05-24 18:34:27 -07:00
Eddie Hung
d15da4bc11
Add more tests
2019-05-24 18:33:18 -07:00
Eddie Hung
4bd9465ed3
Call proc
2019-05-24 18:32:02 -07:00
Eddie Hung
f0c6b73b72
Fix duplicate driver
2019-05-24 17:44:57 -07:00
Eddie Hung
68359bcd6f
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
2019-05-23 13:37:53 -07:00
Eddie Hung
47f9ea142f
Add opt_rmdff tests
2019-05-23 11:26:38 -07:00
Stefan Biereigel
c2caf85f7c
add simple test case for wand/wor
2019-05-23 13:57:27 +02:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Maciej Kurc
1f52332b8d
Added tests for Verilog frontent for attributes on parameters and localparams
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00
Clifford Wolf
b7ec698d40
Add test case from #997
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:58:04 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d97c644bc1
Add tests/various/chparam.sh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 16:03:15 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
8c6e94d57c
Improve tests/various/specify.ys
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:26:15 +02:00
Eddie Hung
554c58715a
More testing
2019-05-03 15:54:25 -07:00
Eddie Hung
bfb8b3018b
Fix spacing
2019-05-03 15:42:02 -07:00
Eddie Hung
09841c2ac1
Add quick-and-dirty specify tests
2019-05-03 15:35:26 -07:00
Eddie Hung
1e5f072c05
iverilog with simcells.v as well
2019-05-03 14:03:51 -07:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Clifford Wolf
71ede7cb05
Merge pull request #976 from YosysHQ/clifford/fix974
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Fix width detection of memory access with bit slice
2019-05-03 15:29:44 +02:00
Clifford Wolf
d2aa123226
Fix typo in tests/svinterfaces/runone.sh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 14:40:51 +02:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Jakob Wenzel
98ffe5fb00
fail svinterfaces testcases on yosys error exit
2019-05-02 09:52:30 +02:00
Jim Lawson
38f5424f92
Fix #938 - Crash occurs in case when use write_firrtl command
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Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
2019-05-01 13:16:01 -07:00
Clifford Wolf
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf
e5cb9435a0
Add additional test cases for for-loops
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:32:07 +02:00
Clifford Wolf
b515fd2d25
Add peepopt_muldiv, fixes #930
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00