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OpenFPGA
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437 Commits

Author SHA1 Message Date
tangxifan 64d8e9663a minor fix to satisfy Fc_in and Fc_out 2019-07-05 13:13:35 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan d64aeef5c4 add profiling to routing compact process 2019-07-03 16:57:34 -06:00
tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W 2019-07-03 16:46:43 -06:00
tangxifan b79d276ea9 add profiling to fpga_x2p_setup 2019-07-03 14:44:54 -06:00
tangxifan d5137eb424 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-03 14:31:18 -06:00
tangxifan 5195faab8b Merge branch 'dev' into tileable_routing 2019-07-03 14:30:39 -06:00
tangxifan 4f3cb0bdf3 added tileable routing chanW adaption to fixed W router 2019-07-03 14:29:50 -06:00
Ganesh Gore 443a73954f Removed all local files 
+ Removed local configurations and scripts from previous commit
 2019-07-03 14:26:06 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev 
- Added spice_tool option in fpga_flow
- Some local customization
 2019-07-03 13:39:52 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 44301bfd77 updated SPICE generator to avoid issues on clb2clb_direct 2019-07-02 09:01:52 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 15c536e9b4 minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
Baudouin Chauviere 04eb6d3488 Correction pre-merge 2019-06-27 14:33:06 -06:00
Ganesh Gore 11e6350214 Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev 2019-06-27 14:22:40 -06:00
Baudouin Chauviere 7c742f1cbb Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
tangxifan 8edd85c9fc keep fixing bugs in verilog SDC generator for tileable CBs 2019-06-26 22:58:52 -06:00
tangxifan 711e369fe7 fixing bugs in the SDC generator and report_timing 2019-06-26 18:09:09 -06:00
tangxifan 0fe54d87d5 fixed a bug in SDC generator for constraining SBs in tileable arch 2019-06-26 17:06:14 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan 7d85eb544d start fixing bugs for SDC generator when using tileable arch 2019-06-26 16:48:17 -06:00
tangxifan f5920c7422 fix bugs in ptc_num using for SB 2019-06-26 16:21:02 -06:00
tangxifan 3d8200e217 critical bug fixed in bitstream generator for compact routing hierarchy 2019-06-26 15:51:11 -06:00
tangxifan d2ed82d14d Merge branch 'tileable_routing' into multimode_clb 2019-06-26 15:00:39 -06:00
tangxifan 57616361c2 fixed critical bugs in cb configuration port indices 2019-06-26 14:58:52 -06:00
Baudouin Chauviere d2bd2be76b Warnings correction in the make sequence 2019-06-26 14:33:12 -06:00
Baudouin Chauviere 87ddca9f57 commiting current work. Stable but function not implemented yet 2019-06-26 14:22:02 -06:00
tangxifan 42f85004b6 fix bugs in finding the ending SB of a rr_node 2019-06-26 14:13:41 -06:00
tangxifan 9b6a4b39bb Merge branch 'tileable_routing' into multimode_clb 2019-06-26 11:36:08 -06:00
tangxifan c879e7f6c5 fixed a critical bug when instanciating Connection blocks 2019-06-26 11:33:02 -06:00
Baudouin Chauviere b7c2954b91 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-26 10:51:55 -06:00
Baudouin Chauviere 8f21a3b177 Memory leakage correction 2019-06-26 10:50:38 -06:00
tangxifan d50fb7ee19 fixed the bug in determine passing wires for rr_gsb 2019-06-26 10:50:23 -06:00
AurelienUoU ec504049ef Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
tangxifan a3670bb752 Merge branch 'multimode_clb' into tileable_routing 2019-06-26 09:45:04 -06:00
Baudouin Chauviere 56557b94e7 Bug Fix 2019-06-26 08:53:46 -06:00
tangxifan 3c0ef2067d fixed critical bugs in pass_tracks identification and update regression test for tileable arch 2019-06-25 21:59:38 -06:00
Baudouin Chauviere bb250ddef9 Bug fix in cpp 2019-06-25 16:47:10 -06:00
Ganesh Gore 6d3066174b Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev 2019-06-25 15:12:13 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
Baudouin Chauviere 332ce17f03 Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
tangxifan a88263a4c2 update rr_block writer to include IPINs in XML files 2019-06-25 11:17:22 -06:00
tangxifan 785b560bd5 sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now 2019-06-24 22:46:56 -06:00
tangxifan fd301eeb66 many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
tangxifan 0d62661c71 bug fixing and spot critical bugs in directlist parser 2019-06-23 20:52:38 -06:00
tangxifan cdd4af9c58 vpr likes the tileable rr_graph while fpga_x2p does not 2019-06-23 18:11:13 -06:00
tangxifan 59df305668 bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00
tangxifan 2837f44df2 bug fixing for tileable rr_graph generator. 2019-06-22 20:41:06 -06:00
tangxifan 7c38b32eb1 keep bug fixing for tileable rr_graph generator 2019-06-21 22:51:11 -06:00
tangxifan 1b91c32121 Merge branch 'multimode_clb' into tileable_routing 2019-06-21 17:59:55 -06:00
tangxifan 41954056ce many bug fixing for tileable rr_graph generator. Still debugging 2019-06-21 17:58:46 -06:00
AurelienUoU 0a42f6a796 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-21 15:47:14 -06:00
AurelienUoU c0d7099cd6 Allow CB on top of blocks with height > 1 2019-06-21 15:46:05 -06:00
tangxifan d48fd959a9 keep bug fixing for tileable rr_graph generator 2019-06-20 22:30:26 -06:00
tangxifan 548242b368 plug-in tileable rr generator which can be enable by a XML property 2019-06-20 21:06:26 -06:00
tangxifan cf82d87e11 Merge branch 'multimode_clb' into tileable_routing 2019-06-20 18:18:20 -06:00
tangxifan baab9c4a21 basically finished the coding of tileable rr_graph generator. testing to go 2019-06-20 18:17:07 -06:00
Baudouin Chauviere be25b6dd66 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-20 14:11:03 -06:00
Baudouin Chauviere 3bd6c40a10 Report timing modified to have only one liners 2019-06-20 14:10:39 -06:00
AurelienUoU a7502bb43b Avoid configuration bits for module wihch don't require them 2019-06-20 09:40:41 -06:00
tangxifan e7f2bd3b7c Merge branch 'multimode_clb' into tileable_routing 2019-06-19 21:31:54 -06:00
tangxifan 2f15d2d13c keep developing tileable rr_graph, track2ipin and opin2track to go 2019-06-19 21:30:16 -06:00
AurelienUoU ff00e4c79c Free only if it's possible to free 2019-06-19 16:15:30 -06:00
tangxifan ba15358564 developing ipin2track mapping for tiles 2019-06-18 18:06:21 -06:00
tangxifan 9ca1b42f4c developing switch block pattern for tileable routing architecture 2019-06-18 16:52:42 -06:00
tangxifan 352c97302b start building object GSB graph 2019-06-17 22:10:30 -06:00
tangxifan f4191315da use rr_gsb to build edges of rr_graph 2019-06-17 18:01:45 -06:00
tangxifan 51ff150a77 bug fixing in tileable rr_graph generator 2019-06-17 10:16:08 -06:00
tangxifan 0d14fef53e bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator 2019-06-16 23:02:18 -06:00
tangxifan 04ffb99ca6 Merge branch 'multimode_clb' into tileable_routing 2019-06-16 16:01:30 -06:00
Baudouin Chauviere 57a4ad1f99 Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
tangxifan 1af3b5ef55 set chan_rr_nodes in tileable rr_graph builder 2019-06-16 14:23:19 -06:00
tangxifan 8c9cc003ea developing routing track rr_node set up in tileable routing architecture 2019-06-15 18:11:08 -06:00
Xifan Tang 155c8d4924 fix CMakeList bug in disabling VPR graphics 2019-06-15 13:21:25 -06:00
tangxifan d19b470b33 Merge branch 'tileable_routing' into multimode_clb 
Conflicts:
	vpr7_x2p/vpr/regression_verilog.sh
 2019-06-15 12:25:30 -06:00
tangxifan c8bf456097 bug fixing for memory leaking in allocating pb_rr_graph and power estimation 2019-06-15 12:23:36 -06:00
tangxifan d3296d0975 developing tileable rr_graph builder 2019-06-14 22:35:42 -06:00
tangxifan a33627606e developing tileable routing track arrangement 2019-06-14 17:35:40 -06:00
AurelienUoU 29dadc51b4 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-14 11:46:02 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan 4d2a3680be support bus explicit port mapping to standard cells (for BRAMs) 2019-06-14 11:09:15 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
tangxifan 5f61cd8876 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 
Conflicts:
	vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
 2019-06-13 16:32:39 -06:00
tangxifan af1628abfe use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
tangxifan dddbbac85c merge from multimode_clb bug fixing 2019-06-13 15:59:34 -06:00
AurelienUoU 15b4cc9ecb Error correction in memory generation for pb_types without modes 2019-06-13 15:34:25 -06:00
tangxifan 43128ad3f0 fix a bug in formal verification port for memory bank configuration circuits 2019-06-13 15:33:13 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tangxifan 5ae4dec0af fix bugs in CMakeList on enable/disable VPR Graphics 2019-06-12 22:48:00 -06:00
tangxifan 1d00e3665b start developing tileable_rr_graph_builder 2019-06-11 16:50:40 -06:00
tangxifan 65b5454f3a start developing tileable_rr_graph_builder 2019-06-11 16:49:10 -06:00
AurelienUoU bf13c1f731 Add a script to create a new file with correct path rather than overwrite the existing 2019-06-11 14:28:58 -06:00
Ganesh Gore 1da363f7f1 Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev 2019-06-11 11:59:54 -06:00
tangxifan 7245917b9c fix a bug for iopad SPICE generation 2019-06-11 11:43:56 -06:00
Ganesh Gore 1093e341a8 Added additional architecure files 2019-06-11 11:26:44 -06:00
tangxifan 1776ae3ec8 add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
tangxifan 8e3ad675e0 use sstream for rr_block verilog writer 2019-06-10 16:23:35 -06:00
tangxifan 009e5244d3 minor fix on the port direction of configuration peripherals for memory decoders 2019-06-10 15:39:35 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan e4f70771a2 updated SDC generator to embrace the RRGSB data structure 2019-06-10 14:47:27 -06:00
tangxifan 8a8f4153ce use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB 2019-06-10 12:50:10 -06:00
tangxifan e31407f693 start cleaning up SDC generator with new RRGSB data structure 2019-06-10 10:57:26 -06:00
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
Xifan Tang 61e359efc5 Enable an option to disable/enable graphics in VPR compilation 2019-06-08 15:08:17 -06:00
tangxifan 90696def6d remove vpr Makefile 2019-06-07 23:44:39 -06:00
tangxifan d737c4ff46 fix path in regression test! TODO: must keep a duplicated copy for template.xml 2019-06-07 23:31:42 -06:00
tangxifan f5b6ee6adf update travis configuration and clean up repository 2019-06-07 22:19:11 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
tangxifan 44ce0e8834 update gsb unique module detection and fix formal verification port direction 2019-06-07 17:18:38 -06:00
tangxifan 24d53390d8 clean up DeviceRRGSB internal data and member functions 2019-06-07 14:45:56 -06:00
tangxifan c9f810ceb6 update rr_gsb to build connection blocks 2019-06-07 11:01:55 -06:00
tangxifan 472aff5acb add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB 2019-06-06 23:45:21 -06:00
tangxifan ce9fc5696c rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
tangxifan 8c1e7b799f fixed critical bugs in Connection Block Unique Module detection 2019-06-06 16:31:50 -06:00
tangxifan 4f543c510c Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-06 12:50:03 -06:00
tangxifan 873e4d989f fine-tuning Verilog format and node addition to rr_blocks 2019-06-06 12:48:41 -06:00
AurelienUoU 182d49da45 Update regression test scripts 2019-06-06 11:47:51 -06:00
tangxifan c2de0eefb1 fix redundant comma in SB Verilog module 2019-06-06 09:15:05 -06:00
tangxifan b9e1b1afc4 fix a critical bug in num_reserved_sram_ports 2019-06-05 17:31:01 -06:00
tangxifan aaf8d23971 fix critical bugs in routing submodules 2019-06-05 16:43:18 -06:00
tangxifan 01e075377d fix typo in Verilog generation 2019-06-05 15:30:34 -06:00
tangxifan 21d0cb52bc Merge remote-tracking branch 'origin' into tileable_sb 2019-06-05 13:31:49 -06:00
tangxifan 24ca3104b0 fix minor bugs in Switch Block submodules 2019-06-05 13:30:55 -06:00
tangxifan 0f87ae9886 support switch block submodule Verilog generation by segments 2019-06-05 12:56:05 -06:00
AurelienUoU 84fabbd43b Fix sdc analysis bug related to virtual nodes + add the option in regression test 2019-06-05 12:10:28 -06:00
Baudouin Chauviere d24488092d Fix bug 2019-06-05 11:40:04 -06:00
tangxifan c2d8fa00ba add rr_block unique_side_module verilog generation 2019-06-04 17:47:40 -06:00
AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path 2019-06-04 15:21:15 -06:00
tangxifan 98b82c17be bug fixing for clear RRSwitchBlock 2019-06-04 14:02:49 -06:00
tangxifan 2c6780ab92 add side mirror detection for RRSwitchBlock 2019-06-04 13:01:22 -06:00
AurelienUoU 813470d459 Test Cmake fix 2019-06-03 10:31:44 -06:00
AurelienUoU 7368e6d7e4 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-31 11:01:07 -06:00
AurelienUoU 737300eb54 Fix regression test 2019-05-31 11:00:30 -06:00
Baudouin Chauviere 1932d00309 Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
AurelienUoU 46fa1197b0 Test reading tech file 2019-05-29 16:43:56 -06:00
AurelienUoU 74ee6bad7f Update spice path in architecture 2019-05-29 10:08:58 -06:00
tangxifan 5b15a746d3 add num_driver_nodes to Switch Block XML writter 2019-05-28 20:52:33 -06:00
tangxifan 5ed076dfb4 fixed a critical bug in rotating 2019-05-28 17:55:09 -06:00
tangxifan 9cc5518d5a keep adding segment information for SB XML outputter 2019-05-28 15:59:55 -06:00
tangxifan e7e18eb4c1 Add more information in SB XML outputter 2019-05-28 15:56:41 -06:00
tangxifan ca363da30c add options to specify output directory of SB XML 2019-05-28 15:19:10 -06:00
tangxifan 6b51b42ee7 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 14:53:44 -06:00
tangxifan af91fca1e0 add rr_blocks XML writer to help debugging Switch Block Rotation 2019-05-28 14:52:44 -06:00
Baudouin Chauviere 3da216f297 correction Null issue for the flat model 2019-05-28 14:15:24 -06:00
AurelienUoU ffdcd4bb9c Path correction 2 2019-05-28 11:59:09 -06:00
tangxifan c75ffa858b Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 11:26:16 -06:00
tangxifan 6f30d3ad05 support rotation on segment groups inside RRChan and improve rotatable mirror searching 2019-05-28 11:25:16 -06:00
AurelienUoU 20f80a73e7 Correct path to tech files 2019-05-28 11:24:03 -06:00
tangxifan 0f5666ea11 fixed the bug in mirror node direction 2019-05-27 21:58:21 -06:00
tangxifan eece161d58 keep debugging on Switch Block rotation 2019-05-27 21:10:30 -06:00
tangxifan 5720217cfd Add copy constructor for RRChan, RRSwitchBlock etc. 2019-05-27 15:44:34 -06:00
tangxifan 1bea9870fc developed new rotating methods for RRSwitchBlocks, debugging ongoing 2019-05-26 23:35:30 -06:00
tangxifan 4b852afeac skip rotating mirror detection which is too time-consuming 2019-05-25 23:41:46 -06:00
tangxifan 22e71f5847 Add rotate one side of switch block functionality 2019-05-25 22:48:07 -06:00
tangxifan 858a323228 Add more support for rotating Switch Blocks 2019-05-25 21:26:35 -06:00
tangxifan 2eab0b1c1c update unique_mirror search algorithm for Switch Blocks 2019-05-25 19:54:15 -06:00
tangxifan d3eae80e64 implemented an native way in finding rotable Switch blocks 2019-05-25 19:37:18 -06:00
tangxifan ae0248fbc6 debugging SwitchBlock rotating 2019-05-24 23:10:30 -06:00
tangxifan 9adc2945c8 add rotate functionality for RRSwitchBlock 2019-05-24 21:40:16 -06:00
tangxifan 02b48d036d clean warnings 2019-05-24 16:48:08 -06:00
tangxifan 2c46da6888 clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
tangxifan 27b996337a fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00
tangxifan 1ade1f1d3f update SDC generator disabled_unused_mux by using RRSwitchBlock 2019-05-24 15:42:00 -06:00
tangxifan f27b88db8d Use RRChan in SDC generator to replace old data structures 2019-05-24 15:34:56 -06:00
tangxifan 27c234711e clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
tangxifan 924136e7a2 Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info 2019-05-24 15:10:08 -06:00
tangxifan 994b90ae53 updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan 8f4f590ff9 update Verilog compact_netlist outputter with RRSwitchBlock classes 2019-05-23 21:52:12 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
tangxifan 4aab93b729 update class rr_switch_block and be ready for updating the downstream verilog generator 2019-05-22 22:04:31 -06:00
tangxifan 502344b13a add missing files 2019-05-22 12:35:12 -06:00
tangxifan efbc454cdd Add Class for RRSwtichBlock and plug-in to replace the old t_sb 2019-05-22 12:34:06 -06:00
tangxifan ec3b4c86c4 update file organization and be ready for SB/CB class 2019-05-21 12:15:38 -06:00
tangxifan 8186d6dd11 reorganize files and clean some warnings 2019-05-21 10:17:54 -06:00
tangxifan b185a17359 add routing_channel unique module generation 2019-05-20 22:33:17 -06:00
giacomin ceee28226e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-20 16:47:07 -06:00
giacomin 8b520349e7 fixed a bug for rram based fpga when using explicit verilog port mapping 2019-05-20 16:44:47 -06:00
AurelienUoU 4f921b03da Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
AurelienUoU f31339bb5c Correctly instantiate script variables 2019-05-16 14:30:16 -06:00
AurelienUoU 57d75520a6 Verilog verification with Travis 2019-05-15 15:57:05 -06:00
AurelienUoU e44e228153 Force graphics to false 2019-05-15 15:01:54 -06:00
AurelienUoU f940c4fd59 Third try to fix issues with graphics on mac 2019-05-15 13:22:14 -06:00
AurelienUoU a55886a4d9 Second try to fix travis autotest adding x11 in macos packages 2019-05-15 09:28:29 -06:00
AurelienUoU 1961b18d14 Fix CMakeList to avoid MacOS build failure 2019-05-14 18:15:13 -06:00
AurelienUoU 99beeb48cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 16:42:27 -06:00
AurelienUoU a3656dde45 Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00