tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
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a8c803f08f
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try to fix bugs in explicit port mapping
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2019-09-02 16:37:43 -06:00 |
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tangxifan
|
d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
|
4490c78195
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-09-02 14:30:55 -06:00 |
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tangxifan
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395bf4fbdf
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refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
Ganesh Gore
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e37ac1a565
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-02 00:19:19 -06:00 |
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Ganesh Gore
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241b001282
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Added openfpga_task doc
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2019-09-01 22:15:53 -06:00 |
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Ganesh Gore
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0439476abe
|
Removed OSX allowed failure from travis
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2019-09-01 00:08:14 -06:00 |
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Ganesh Gore
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ac8cc230ed
|
Added Exit on fail option to travis task run
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2019-08-31 22:58:07 -06:00 |
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Ganesh Gore
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be6b11304e
|
Added travis fold for Python Task [ci skip]
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2019-08-31 22:36:18 -06:00 |
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Ganesh Gore
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ad4c688206
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Added print for JobID to architecture mapping
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2019-08-31 22:04:57 -06:00 |
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Ganesh Gore
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f4e99c150a
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resolve missing variable bug
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2019-08-31 21:55:32 -06:00 |
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Ganesh Gore
|
3d4f7f66fd
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Updated to run with python3
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2019-08-31 21:42:31 -06:00 |
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Ganesh Gore
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d13c6a32ff
|
Test travis cache
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2019-08-31 20:45:54 -06:00 |
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Ganesh Gore
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31c4d40e66
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Updated cache directory variable
|
2019-08-31 20:00:44 -06:00 |
|
Ganesh Gore
|
32d47d6b8b
|
Update document + Travis cache check
|
2019-08-31 16:13:47 -06:00 |
|
Ganesh Gore
|
3ce63e6163
|
Added abc and yosys cache in travis
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2019-08-31 15:26:14 -06:00 |
|
Ganesh Gore
|
06c0dbb328
|
Added docuementation for fpga_flow
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2019-08-31 15:19:34 -06:00 |
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Ganesh Gore
|
02137805c7
|
Added python version check in flow and task scripts
|
2019-08-29 22:14:30 -06:00 |
|
Ganesh Gore
|
a25124b58c
|
Added additional PATH variables
|
2019-08-29 21:37:07 -06:00 |
|
Ganesh Gore
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f54a8522fa
|
Log prints task stats
|
2019-08-27 22:04:32 -06:00 |
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Ganesh Gore
|
903c2b7705
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-27 21:38:17 -06:00 |
|
Ganesh Gore
|
715adc13ff
|
Failed result do not throw error
|
2019-08-27 21:25:38 -06:00 |
|
tangxifan
|
94538b5062
|
add more testing architecture
|
2019-08-27 18:44:58 -06:00 |
|
tangxifan
|
f04565386f
|
refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
|
tangxifan
|
ab6f1a5461
|
add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
|
tangxifan
|
de8a6bc833
|
update regression tests
|
2019-08-26 21:00:15 -06:00 |
|
Ganesh Gore
|
38e1d1bbff
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-25 21:41:38 -06:00 |
|
tangxifan
|
b6617a5adf
|
fix bugs in verilog comment lines
|
2019-08-25 16:37:46 -06:00 |
|
tangxifan
|
14db2bf1a9
|
minor fixing on comment
|
2019-08-25 16:35:49 -06:00 |
|
tangxifan
|
706b7f3427
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-25 15:52:04 -06:00 |
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tangxifan
|
1cfc117b32
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 15:47:57 -06:00 |
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tangxifan
|
056c45321b
|
plug in module manager
|
2019-08-25 15:44:31 -06:00 |
|
tangxifan
|
8fc258cc93
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-25 15:33:37 -06:00 |
|
tangxifan
|
c43fabb43c
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 10:31:45 -06:00 |
|
Ganesh Gore
|
7a3ff94116
|
Added blif task in travis script
|
2019-08-25 01:28:21 -06:00 |
|
Ganesh Gore
|
937ebd1b85
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-08-25 00:53:18 -06:00 |
|
Ganesh Gore
|
c4180fad6d
|
Added .gitignore to build docs locally
|
2019-08-25 00:49:04 -06:00 |
|
Ganesh Gore
|
632c9d6976
|
Added python execution path in config file
|
2019-08-25 00:42:48 -06:00 |
|
Ganesh Gore
|
f558437ae1
|
Added task for vpr_blif flow
|
2019-08-25 00:23:39 -06:00 |
|
tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
|
tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |
|
tangxifan
|
ad06e9c98c
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
|
2019-08-23 18:41:16 -06:00 |
|
tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
1b4de2b335
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-23 16:37:24 -06:00 |