tangxifan
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6b5ac2e1ef
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add timing graph builder for circuit models
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2019-08-09 12:45:03 -06:00 |
Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |
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tangxifan
|
c8d04c4f00
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plug in fast look-up builder
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2019-08-08 21:20:28 -06:00 |
|
Ganesh Gore
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0cc439f76c
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Working lattice benchmark unclean commit
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2019-08-08 18:08:39 -06:00 |
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tangxifan
|
158c67075e
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built a conversion from spice_models to circuit_library and plug in
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2019-08-08 17:25:27 -06:00 |
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tangxifan
|
e19485bbb7
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add more accessors and more to be added when plug into framework
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2019-08-08 14:16:29 -06:00 |
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tangxifan
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ad8c33e1ba
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complete the mutators
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2019-08-08 11:33:11 -06:00 |
|
tangxifan
|
5b0c9572c3
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add mutators for delay_info
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2019-08-07 21:19:16 -06:00 |
|
tangxifan
|
03a64e2ad8
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complete the mutators for ports
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2019-08-07 20:54:27 -06:00 |
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tangxifan
|
9f8c7a3fc7
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adding port mutators
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2019-08-07 17:47:39 -06:00 |
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tangxifan
|
ed4642a23f
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adding basic mutators
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2019-08-07 17:12:05 -06:00 |
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tangxifan
|
38962c4607
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adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
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tangxifan
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74da4ed51a
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start creating the class for circuit models
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2019-08-07 11:38:45 -06:00 |
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tangxifan
|
f57495feba
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Now we can also auto-generate the Verilog for a mux2 std cell
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2019-08-06 15:19:01 -06:00 |
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tangxifan
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55bfaf271d
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Merge branch 'dev' into std_map_support
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2019-08-06 14:38:19 -06:00 |
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tangxifan
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afa468a442
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hotfix in minor Verilog generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
|
b207050b03
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minor fix in documentation
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2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
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bug fixing for local encoder's bitstream generation
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2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
fc93a4941a
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update documentation
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
7603850d72
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complete documentation for new features
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
3a490fdd59
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bug fixing on the port map alignment
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
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bug fixing and get ready for testing
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
c08c136844
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set a working range for the encoders
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
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updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
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add Verilog generation for local encoders, bitstream upgrade TODO
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
003883b13b
|
implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
33f3a991b5
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init effort to start developing mux local encoders
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2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
7748340314
|
hot fix on tutorial
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
2291c52fab
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-30 16:54:55 -06:00 |
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tangxifan
|
8a046394f8
|
add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
AurelienUoU
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40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-29 11:45:23 -06:00 |
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tangxifan
|
716c3c63c3
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-27 15:06:06 -06:00 |
|
AurelienUoU
|
7d469d8b4f
|
Docker try 2
|
2019-07-22 13:06:46 -06:00 |
|
AurelienUoU
|
52b754f9c1
|
Update
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2019-07-22 10:14:03 -06:00 |
|
AurelienUoU
|
0854161a63
|
Docker update
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2019-07-22 09:42:31 -06:00 |
|
AurelienUoU
|
64a67dceaf
|
Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
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2019-07-18 16:34:47 -06:00 |
|
AurelienUoU
|
f4e999ef6d
|
Correct error in demo, set a new generated ff_${benchmark}.v file rather than overwrite
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2019-07-18 16:33:23 -06:00 |
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tangxifan
|
73d6d5264a
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-18 13:40:19 -06:00 |
|
tangxifan
|
434c0d9683
|
hot fix on tutorial
|
2019-07-18 13:39:47 -06:00 |
|
Xifan Tang
|
173440ffc3
|
retry
|
2019-07-17 18:46:54 -04:00 |
|
Xifan Tang
|
8226f42d3d
|
use hfill to place image inline
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2019-07-17 18:46:14 -04:00 |
|
Xifan Tang
|
a80199057d
|
logo placement
|
2019-07-17 18:43:17 -04:00 |
|
Xifan Tang
|
37abd8af40
|
try to place inline logo
|
2019-07-17 18:40:26 -04:00 |
|
Xifan Tang
|
f3ed949c4b
|
retry placing images
|
2019-07-17 18:36:49 -04:00 |
|
Xifan Tang
|
b104de0263
|
resize logo again
|
2019-07-17 17:56:06 -04:00 |
|
Xifan Tang
|
b850610cea
|
resize logo to fit
|
2019-07-17 17:55:10 -04:00 |
|
Xifan Tang
|
17308621bd
|
resize logo on README
|
2019-07-17 17:53:36 -04:00 |
|
Xifan Tang
|
af335dff66
|
Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
|
2019-07-17 17:51:45 -04:00 |
|
Xifan Tang
|
afd78604c9
|
Merge branch 'dev' into documentation: resolved conflicts and add logo files
|
2019-07-17 17:50:11 -04:00 |