Working lattice benchmark unclean commit
This commit is contained in:
Ganesh Gore
parent
57ad71438b
commit
0cc439f76c
|
|
@ -35,4 +35,6 @@ vpr7_x2p/pcre/pcredemo
|
|||
|
||||
# Some local temporary files
|
||||
.vscode
|
||||
*_local.bat
|
||||
*_local.bat
|
||||
fpga_flow/csv_rpts
|
||||
tmp/
|
||||
26
Dockerfile
26
Dockerfile
|
|
@ -1,10 +1,16 @@
|
|||
FROM ubuntu:16.04
|
||||
|
||||
RUN apt-get update -qq -y
|
||||
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
|
||||
|
||||
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
|
||||
|
||||
RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
|
||||
RUN cd OpenFPGA && make
|
||||
|
||||
FROM ubuntu:16.04
|
||||
|
||||
RUN apt-get update -qq -y
|
||||
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
|
||||
|
||||
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
|
||||
|
||||
RUN mkdir -p /release /dev
|
||||
|
||||
RUN cd release && git clone --single-branch --branch documentation https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
|
||||
|
||||
RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -CMAKE_BUILD_TYPE=debug && make
|
||||
|
||||
RUN rm -rf /var/lib/apt/lists/*
|
||||
|
||||
WORKDIR /release/OpenFPGA
|
||||
|
|
@ -0,0 +1 @@
|
|||
results
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout auto="1.0"/>
|
||||
<!-- <layout width="2" height="2"/> -->
|
||||
<!-- <layout width="20" height="20"/> -->
|
||||
|
||||
<!--mrFPGA_settings-->
|
||||
<!-- below is the timing parameters for a single memristor device (or so called RRAM) -->
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
<cmos abs_variation="0.1" num_sigma="1"/>
|
||||
<rram abs_variation="0.1" num_sigma="1"/>
|
||||
</monte_carlo>
|
||||
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
|
||||
<measure sim_num_clock_cycle="auto" accuracy="1e-12" accuracy_type="abs">
|
||||
<slew>
|
||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
||||
|
|
@ -142,7 +142,7 @@
|
|||
<!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</spice_model>
|
||||
<spice_model type="mux" name="mux_1level" prefix="mux_1level" is_default="1" dump_structural_verilog="true">
|
||||
<!--design_technology type="cmos" structure="one-level"/-->
|
||||
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
|
||||
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
|
||||
<input_buffer exist="on" spice_model_name="INVTX1"/>
|
||||
<output_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -155,7 +155,7 @@
|
|||
<port type="sram" prefix="sram" size="1" spice_model_name="sram6T_rram"/>
|
||||
</spice_model>
|
||||
<spice_model type="mux" name="mux_1level_tapbuf4" prefix="mux_1level_tapbuf4" is_default="0" dump_structural_verilog="true">
|
||||
<!--design_technology type="cmos" structure="one-level"/-->
|
||||
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
|
||||
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
|
||||
<input_buffer exist="on" spice_model_name="INVTX1"/>
|
||||
<output_buffer exist="on" spice_model_name="tap_buf4"/>
|
||||
|
|
@ -168,7 +168,7 @@
|
|||
<port type="sram" prefix="sram" size="1" spice_model_name="sram6T_rram"/>
|
||||
</spice_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="/home/u1235811/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="VerilogNetlists/ff.v">
|
||||
<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="VerilogNetlists/ff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
<output_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -191,7 +191,7 @@
|
|||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="64" spice_model_name="sram6T_rram" default_val="1"/>
|
||||
</spice_model>
|
||||
<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/home/u1235811/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
|
||||
<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
<output_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -199,7 +199,7 @@
|
|||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="2"/>
|
||||
</spice_model>
|
||||
<spice_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/home/u1235811/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
|
||||
<spice_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
|
||||
<!--design_technology type="cmos"/-->
|
||||
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
|
||||
<input_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -212,7 +212,7 @@
|
|||
<port type="bl" prefix="bl" size="3" default_val="0" inv_spice_model_name="INVD1BWP"/>
|
||||
<port type="wl" prefix="wl" size="3" default_val="0" inv_spice_model_name="INVD1BWP"/>
|
||||
</spice_model>
|
||||
<spice_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/home/u1235811/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
|
||||
<spice_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
<output_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -225,7 +225,7 @@
|
|||
<port type="wl" prefix="wl" size="1"/>
|
||||
</spice_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<spice_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/home/u1235811/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="VerilogNetlists/ff.v">
|
||||
<spice_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="VerilogNetlists/ff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
<output_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -237,7 +237,7 @@
|
|||
<port type="output" prefix="Qb" size="1"/>
|
||||
<port type="clock" prefix="clk" size="1"/>
|
||||
</spice_model>
|
||||
<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/home/u1235811/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="VerilogNetlists/io.v">
|
||||
<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="VerilogNetlists/io.v">
|
||||
<!--design_technology type="cmos"/-->
|
||||
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
|
||||
<input_buffer exist="on" spice_model_name="INVD1BWP"/>
|
||||
|
|
@ -252,28 +252,8 @@
|
|||
</module_spice_models>
|
||||
</spice_settings>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="3"/>
|
||||
<timing C_ipin_cblock="596e-18" T_ipin_cblock="45.54e-12"/>
|
||||
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<!--sram area="6" organization="standalone" spice_model_name="sram6T"-->
|
||||
<!--sram area="6" organization="scan-chain" spice_model_name="sc_dff"-->
|
||||
|
|
@ -334,14 +314,6 @@
|
|||
<cb type="pattern">1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<!-- <directlist>
|
||||
</directlist> -->
|
||||
<!--switch_segment_patterns>
|
||||
<pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
|
||||
<unbuf_mux name="1"/>
|
||||
<sb type ="pattern">0 1</sb>
|
||||
</pattern>
|
||||
</switch_segment_patterns-->
|
||||
|
||||
<complexblocklist>
|
||||
|
||||
|
|
@ -457,12 +429,12 @@
|
|||
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||
127e-12
|
||||
127e-12
|
||||
127e-12
|
||||
127e-12
|
||||
127e-12
|
||||
127e-12
|
||||
2.094e-09
|
||||
2.094e-09
|
||||
2.094e-09
|
||||
2.094e-09
|
||||
2.094e-09
|
||||
2.094e-09
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
|
||||
|
|
@ -483,9 +455,8 @@
|
|||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out" spice_model_name="mux_1level">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="42.24e-12" in_port="lut6.out" out_port="ble6.out" />
|
||||
<delay_constant max="42.24e-12" in_port="ff.Q" out_port="ble6.out" />
|
||||
<delay_constant max="2.736e-10" in_port="lut6.out" out_port="ble6.out" />
|
||||
<delay_constant max="2.736e-10" in_port="ff.Q" out_port="ble6.out" />
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
|
|
@ -508,8 +479,8 @@
|
|||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" spice_model_name="mux_1level">
|
||||
<delay_constant max="21.4e-12" in_port="clb.I" out_port="fle[9:0].in" />
|
||||
<delay_constant max="21.4e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
|
||||
<delay_constant max="1.0877e-09" in_port="clb.I" out_port="fle[9:0].in" />
|
||||
<delay_constant max="1.0877e-09" in_port="fle[9:0].out" out_port="fle[9:0].in" />
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||
</complete>
|
||||
|
|
|
|||
|
|
@ -1,2 +1,6 @@
|
|||
# Circuit Names, fixed routing channel width,
|
||||
PID/*.v, 120
|
||||
# PID/*.v, 120
|
||||
up_counter/*.v, 30
|
||||
# MultiBitAdder/*.v, 30
|
||||
# i2c_master_top/*.v, 40
|
||||
# asynch_fifo/*.v, 30
|
||||
|
|
@ -1,8 +1,9 @@
|
|||
# Standard Configuration Example
|
||||
[dir_path]
|
||||
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
|
||||
benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller
|
||||
yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
|
||||
benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example
|
||||
# yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
|
||||
yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys
|
||||
odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
|
||||
cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
|
||||
abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
|
||||
|
|
@ -12,7 +13,7 @@ mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
|
|||
m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
|
||||
mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
|
||||
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
|
||||
rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results
|
||||
rpt_dir = /var/tmp/Openfpga/results
|
||||
ace_path = OPENFPGAPATHKEYWORD/ace2/ace
|
||||
|
||||
[flow_conf]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
# Circuit Names, fixed routing channel width,
|
||||
# PID/*.v, 120
|
||||
up_counter/*.v, 30
|
||||
# MultiBitAdder/*.v, 30
|
||||
# i2c_master_top/*.v, 40
|
||||
# asynch_fifo/*.v, 30
|
||||
|
|
@ -4,7 +4,24 @@ set -e
|
|||
# Make sure a clear start
|
||||
default_task='lattice_benchmark'
|
||||
pwd_path="$PWD"
|
||||
task_name=${1:-$default_task} # run task defined in argument else run default task
|
||||
|
||||
# ========================= Read command argument =========================
|
||||
usage() { echo "Usage: $0 [-b <benchmark_name>] [-s] run spice only [-p] run vpr only " 1>&2; exit 1; }
|
||||
|
||||
while getopts ":b:vpr:spice:" o; do
|
||||
case "${o}" in
|
||||
b)
|
||||
bench=${OPTARG};;
|
||||
v)
|
||||
vpr=1;;
|
||||
s)
|
||||
spice=1;;
|
||||
esac
|
||||
done
|
||||
# ==========================================================================
|
||||
|
||||
task_name=${bench:-$default_task} # run task defined in argument else run default task
|
||||
echo "Running task ${task_name}"
|
||||
config_file="$PWD/configs/${task_name}.conf"
|
||||
bench_txt="$PWD/benchmarks/List/${task_name}.txt"
|
||||
rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv"
|
||||
|
|
@ -16,22 +33,45 @@ config_file_final=$(echo ${config_file/.conf/_final.conf})
|
|||
|
||||
# List of argument passed to FPGA flow
|
||||
vpr_config_flags=(
|
||||
'-N 10'
|
||||
'-K 6'
|
||||
'-ace_d 0.5'
|
||||
'-multi_thread 1'
|
||||
'-vpr_fpga_x2p_rename_illegal_port'
|
||||
'-vpr_fpga_verilog'
|
||||
'-vpr_fpga_bitstream_generator'
|
||||
'-vpr_fpga_verilog_print_autocheck_top_testbench'
|
||||
'-vpr_fpga_verilog_include_timing'
|
||||
'-vpr_fpga_verilog_include_signal_init'
|
||||
'-vpr_fpga_verilog_formal_verification_top_netlist'
|
||||
'-fix_route_chan_width'
|
||||
'-vpr_fpga_verilog_include_icarus_simulator'
|
||||
'-power'
|
||||
"-conf ${config_file_final}"
|
||||
"-benchmark ${bench_txt}"
|
||||
"-rpt ${rpt_file}"
|
||||
"-vpr_fpga_verilog_dir ${verilog_path}"
|
||||
"-N 10"
|
||||
"-K 6"
|
||||
"-remove_designs"
|
||||
"-ace_d 0.5"
|
||||
"-multi_thread 1"
|
||||
# "-route_chan_width 10"
|
||||
"-vpr_fpga_x2p_rename_illegal_port"
|
||||
"-vpr_fpga_verilog"
|
||||
"-vpr_fpga_bitstream_generator"
|
||||
"-vpr_fpga_verilog_print_autocheck_top_testbench"
|
||||
"-vpr_fpga_verilog_include_timing"
|
||||
"-vpr_fpga_verilog_include_signal_init"
|
||||
"-vpr_fpga_verilog_formal_verification_top_netlist"
|
||||
"-fix_route_chan_width"
|
||||
# "-vpr_fpga_verilog_include_icarus_simulator"
|
||||
"-power"
|
||||
"-vpr_fpga_spice spice_taskfile"
|
||||
"-vpr_fpga_spice_simulator_path /uusoc/facility/cad_tools/Synopsys/lnis_tools/hspice/P-2019.06/hspice/bin/"
|
||||
# "-vpr_fpga_spice_print_top_tb"
|
||||
"-vpr_fpga_spice_print_component_tb",
|
||||
# "-vpr_fpga_spice_print_grid_tb"
|
||||
)
|
||||
|
||||
spice_config_flags=(
|
||||
"-conf /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/vpr_fpga_spice_conf/sample.conf"
|
||||
"-task /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/scripts/spice_taskfile_yosys_vpr.txt"
|
||||
"-rpt ${rpt_file/.csv/_spice_result.csv}"
|
||||
"-multi_thread 10"
|
||||
# "-parse_grid_tb"
|
||||
"-parse_pb_mux_tb"
|
||||
"-parse_cb_mux_tb"
|
||||
"-parse_sb_mux_tb"
|
||||
"-parse_lut_tb"
|
||||
# "-parse_hardlogic_tb"
|
||||
)
|
||||
# vpr_config_flags+=("$@") # Append provided arguments
|
||||
|
||||
#=============== Argument Sanity Check =====================
|
||||
#Check if script running in correct (OpenFPGA/fpga_flow) folder
|
||||
|
|
@ -63,9 +103,19 @@ sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_f
|
|||
#==================Clean result, change directory and execute ===============
|
||||
cd ${pwd_path}/scripts
|
||||
|
||||
# perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -vpr_fpga_verilog_dir $verilog_path $(echo "${vpr_config_flags[@]}")
|
||||
if [[ -n "$vpr" ]]; then
|
||||
# Create echo and execute VPR command
|
||||
command="perl fpga_flow.pl $(echo ${vpr_config_flags[@]})"
|
||||
echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n"
|
||||
eval ${command}
|
||||
fi
|
||||
|
||||
perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power
|
||||
if [[ -n "$spice" ]]; then
|
||||
# Create echo and SPICE Execution
|
||||
command="perl run_fpga_spice.pl $(echo ${spice_config_flags[@]})"
|
||||
echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n"
|
||||
eval ${command}
|
||||
fi
|
||||
|
||||
echo "Netlists successfully generated and simulated"
|
||||
exit 0
|
||||
exit 0
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
#!usr/bin/perl -w
|
||||
#!/usr/bin/perl -w
|
||||
# use the strict mode
|
||||
use strict;
|
||||
# Use the Shell enviornment
|
||||
|
|
@ -1182,6 +1182,7 @@ sub run_odin2($ $ $) {
|
|||
}
|
||||
|
||||
sub run_pro_blif_3arg($ $ $) {
|
||||
# Adopt blif format
|
||||
my ($abc_blif_out_bak, $abc_blif_out, $initial_blif) = @_;
|
||||
my ($pro_blif_path) = ($conf_ptr->{dir_path}->{script_base}->{val});
|
||||
|
||||
|
|
@ -1301,7 +1302,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
|
|||
{
|
||||
my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_;
|
||||
my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val});
|
||||
|
||||
|
||||
my ($power_opts);
|
||||
if ("on" eq $opt_ptr->{power}) {
|
||||
$power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}";
|
||||
|
|
@ -1460,7 +1461,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
|
|||
# foreach my $file (0..$#files){
|
||||
# print "$files[$file]\t";
|
||||
# }
|
||||
3 print "\n";
|
||||
# print "\n";
|
||||
#}
|
||||
chdir $cwd;
|
||||
}
|
||||
|
|
@ -1765,7 +1766,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) {
|
|||
print "INFO: try route_chan_width($min_chan_width) success!\n";
|
||||
last; #Jump out
|
||||
} elsif ($max_route_width_retry < $min_chan_width) {
|
||||
# I set a threshold of 1000 as it is the limit of VPR
|
||||
# I set a threshold of 1000 as it is the limit of VPR
|
||||
die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $min_chan_width!\n";
|
||||
} else {
|
||||
print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n";
|
||||
|
|
@ -1791,7 +1792,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) {
|
|||
print "INFO: try route_chan_width($fix_chan_width) success!\n";
|
||||
last; #Jump out
|
||||
} elsif ($max_route_width_retry < $fix_chan_width) {
|
||||
# I set a threshold of 1000 as it is the limit of VPR
|
||||
# I set a threshold of 1000 as it is the limit of VPR
|
||||
die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $fix_chan_width!\n";
|
||||
} else {
|
||||
print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n";
|
||||
|
|
@ -2994,11 +2995,11 @@ sub gen_csv_rpt_vtr_flow($ $)
|
|||
my @keywords;
|
||||
my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val});
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
# adapt to matlab format if the option is enabled
|
||||
if ("on" eq $opt_ptr->{matlab_rpt}) {
|
||||
# Print the data name
|
||||
# Print the data name
|
||||
print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n";
|
||||
# We will set the stats line to be commented
|
||||
# We will set the stats line to be commented
|
||||
print $CSVFH "%";
|
||||
}
|
||||
|
||||
|
|
@ -3029,7 +3030,7 @@ sub gen_csv_rpt_vtr_flow($ $)
|
|||
print $CSVFH "\n";
|
||||
# Check log/stats one by one
|
||||
foreach $tmp(@benchmark_names) {
|
||||
$tmp =~ s/\.v$//g;
|
||||
$tmp =~ s/\.v$//g;
|
||||
print $CSVFH "$tmp";
|
||||
print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}";
|
||||
if ("on" eq $opt_ptr->{min_route_chan_width}) {
|
||||
|
|
@ -3078,12 +3079,12 @@ sub gen_csv_rpt_yosys_vpr_flow($ $)
|
|||
my ($tmp,$ikw,$tmpkw);
|
||||
my @keywords;
|
||||
my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val});
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
if ("on" eq $opt_ptr->{matlab_rpt}) {
|
||||
# Print the data name
|
||||
# Print the data name
|
||||
print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n";
|
||||
# We will set the stats line to be commented
|
||||
# We will set the stats line to be commented
|
||||
print $CSVFH "%";
|
||||
}
|
||||
|
||||
|
|
@ -3117,9 +3118,9 @@ sub gen_csv_rpt_yosys_vpr_flow($ $)
|
|||
my @tokens = split('/', $tmp);
|
||||
$tmp = $tokens[0];
|
||||
|
||||
# For matlab script, we use {} for string
|
||||
# For matlab script, we use {} for string
|
||||
if ("on" eq $opt_ptr->{matlab_rpt}) {
|
||||
print $CSVFH "{'$tmp'}";
|
||||
print $CSVFH "{'$tmp'}";
|
||||
} else {
|
||||
print $CSVFH "$tmp";
|
||||
}
|
||||
|
|
@ -3171,12 +3172,12 @@ sub gen_csv_rpt_standard_flow($ $)
|
|||
my ($tmp,$ikw,$tmpkw);
|
||||
my @keywords;
|
||||
my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val});
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
if ("on" eq $opt_ptr->{matlab_rpt}) {
|
||||
# Print the data name
|
||||
# Print the data name
|
||||
print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n";
|
||||
# We will set the stats line to be commented
|
||||
# We will set the stats line to be commented
|
||||
print $CSVFH "%";
|
||||
}
|
||||
|
||||
|
|
@ -3207,7 +3208,7 @@ sub gen_csv_rpt_standard_flow($ $)
|
|||
print $CSVFH "\n";
|
||||
# Check log/stats one by one
|
||||
foreach $tmp(@benchmark_names) {
|
||||
$tmp =~ s/\.blif$//g;
|
||||
$tmp =~ s/\.blif$//g;
|
||||
print $CSVFH "$tmp";
|
||||
print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}";
|
||||
if ("on" eq $opt_ptr->{min_route_chan_width}) {
|
||||
|
|
@ -3222,7 +3223,7 @@ sub gen_csv_rpt_standard_flow($ $)
|
|||
@keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val};
|
||||
for($ikw=0; $ikw < ($#keywords+1); $ikw++) {
|
||||
$tmpkw = $keywords[$ikw];
|
||||
$tmpkw =~ s/\s//g;
|
||||
$tmpkw =~ s/\s//g;
|
||||
print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}";
|
||||
}
|
||||
if ("on" eq $opt_ptr->{power}) {
|
||||
|
|
@ -3258,11 +3259,11 @@ sub gen_csv_rpt_mpack2_flow($ $)
|
|||
my @keywords;
|
||||
my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val});
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
# adapt to matlab format if the option is enabled
|
||||
if ("on" eq $opt_ptr->{matlab_rpt}) {
|
||||
# Print the data name
|
||||
# Print the data name
|
||||
print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n";
|
||||
# We will set the stats line to be commented
|
||||
# We will set the stats line to be commented
|
||||
print $CSVFH "%";
|
||||
}
|
||||
|
||||
|
|
@ -3298,7 +3299,7 @@ sub gen_csv_rpt_mpack2_flow($ $)
|
|||
print $CSVFH "\n";
|
||||
# Check log/stats one by one
|
||||
foreach $tmp(@benchmark_names) {
|
||||
$tmp =~ s/\.blif$//g;
|
||||
$tmp =~ s/\.blif$//g;
|
||||
print $CSVFH "$tmp";
|
||||
if ("on" eq $opt_ptr->{min_route_chan_width}) {
|
||||
print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}";
|
||||
|
|
@ -3353,11 +3354,11 @@ sub gen_csv_rpt_mpack1_flow($ $)
|
|||
my @keywords;
|
||||
my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val});
|
||||
|
||||
# adapt to matlab format if the option is enabled
|
||||
# adapt to matlab format if the option is enabled
|
||||
if ("on" eq $opt_ptr->{matlab_rpt}) {
|
||||
# Print the data name
|
||||
# Print the data name
|
||||
print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n";
|
||||
# We will set the stats line to be commented
|
||||
# We will set the stats line to be commented
|
||||
print $CSVFH "%";
|
||||
}
|
||||
|
||||
|
|
@ -3383,7 +3384,7 @@ sub gen_csv_rpt_mpack1_flow($ $)
|
|||
print $CSVFH "\n";
|
||||
# Check log/stats one by one
|
||||
foreach $tmp(@benchmark_names) {
|
||||
$tmp =~ s/\.blif$//g;
|
||||
$tmp =~ s/\.blif$//g;
|
||||
print $CSVFH "$tmp";
|
||||
#foreach $tmpkw(@keywords) {
|
||||
print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}";
|
||||
|
|
|
|||
|
|
@ -12,11 +12,11 @@ hardlogic_tb_dir_name = hardlogic_tb
|
|||
cb_tb_dir_name = cb_tb
|
||||
sb_tb_dir_name = sb_tb
|
||||
# Prefix
|
||||
top_tb_prefix =
|
||||
top_tb_prefix =
|
||||
pb_mux_tb_prefix = _grid
|
||||
cb_mux_tb_prefix = _cb
|
||||
sb_mux_tb_prefix = _sb
|
||||
lut_tb_prefix = _grid
|
||||
lut_tb_prefix = _grid
|
||||
hardlogic_tb_prefix = _grid
|
||||
grid_tb_prefix = _grid
|
||||
cb_tb_prefix = _cb
|
||||
|
|
@ -34,35 +34,34 @@ sb_tb_postfix = _sb_testbench.sp
|
|||
|
||||
[task_conf]
|
||||
auto_check = on
|
||||
num_pb_mux_tb =
|
||||
num_cb_mux_tb =
|
||||
num_sb_mux_tb =
|
||||
num_lut_mux_tb =
|
||||
num_hardlogic_tb =
|
||||
num_grid_mux_tb =
|
||||
num_top_tb =
|
||||
num_cb_tb =
|
||||
num_sb_tb =
|
||||
num_pb_mux_tb =
|
||||
num_cb_mux_tb =
|
||||
num_sb_mux_tb =
|
||||
num_lut_mux_tb =
|
||||
num_hardlogic_tb =
|
||||
num_grid_mux_tb =
|
||||
num_top_tb =
|
||||
num_cb_tb =
|
||||
num_sb_tb =
|
||||
|
||||
[csv_tags]
|
||||
#top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_io|leakage_power_local_interc|total_leakage_power_lut5|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs
|
||||
top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_local_interc|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs
|
||||
top_tb_leakage_power_tags = leakage_power_sram_local_routing | leakage_power_sram_luts | leakage_power_sram_cbs | leakage_power_sram_sbs | leakage_power_local_interc | total_leakage_power_lut6 | total_leakage_power_dff | leakage_power_cbs | leakage_power_sbs
|
||||
#top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_io|energy_per_cycle_local_routing|total_energy_per_cycle_lut5|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs
|
||||
top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs #|crit_path_delay
|
||||
pb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_pb_mux
|
||||
cb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_cb_mux
|
||||
sb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_sb_mux
|
||||
pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_pb_mux
|
||||
cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_cb_mux
|
||||
sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_sb_mux
|
||||
lut_tb_leakage_power_tags = leakage_power_sram_luts|total_leakage_power_lut6
|
||||
lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts|total_energy_per_cycle_lut6
|
||||
top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing | energy_per_cycle_sram_luts | energy_per_cycle_sram_cbs | energy_per_cycle_sram_sbs | energy_per_cycle_local_routing | total_energy_per_cycle_lut6 | total_energy_per_cycle_dff | energy_per_cycle_cbs | energy_per_cycle_sbs #|crit_path_delay
|
||||
pb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_pb_mux
|
||||
cb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_cb_mux
|
||||
sb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_sb_mux
|
||||
pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_pb_mux
|
||||
cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_cb_mux
|
||||
sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_sb_mux
|
||||
lut_tb_leakage_power_tags = leakage_power_sram_luts | total_leakage_power_lut6
|
||||
lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts | total_energy_per_cycle_lut6
|
||||
hardlogic_tb_leakage_power_tags = total_leakage_power_dff
|
||||
hardlogic_tb_dynamic_power_tags = total_energy_per_cycle_dff
|
||||
grid_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_local_routing|total_leakage_power_lut6|total_leakage_power_dff
|
||||
grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing|total_energy_per_cycle_sram_luts|total_energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff
|
||||
cb_tb_leakage_power_tags = leakage_power_cb|leakage_power_sram_cb
|
||||
cb_tb_dynamic_power_tags = energy_per_cycle_cb|energy_per_cycle_sram_cb
|
||||
sb_tb_leakage_power_tags = leakage_power_sb|leakage_power_sram_sb
|
||||
sb_tb_dynamic_power_tags = energy_per_cycle_sb|energy_per_cycle_sram_sb
|
||||
|
||||
grid_tb_leakage_power_tags = leakage_power_sram_local_routing | leakage_power_sram_luts | leakage_power_local_routing | total_leakage_power_lut6 | total_leakage_power_dff
|
||||
grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing | total_energy_per_cycle_sram_luts | total_energy_per_cycle_local_routing | total_energy_per_cycle_lut6 | total_energy_per_cycle_dff
|
||||
cb_tb_leakage_power_tags = leakage_power_cb | leakage_power_sram_cb
|
||||
cb_tb_dynamic_power_tags = energy_per_cycle_cb | energy_per_cycle_sram_cb
|
||||
sb_tb_leakage_power_tags = leakage_power_sb | leakage_power_sram_sb
|
||||
sb_tb_dynamic_power_tags = energy_per_cycle_sb | energy_per_cycle_sram_sb
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh
|
||||
docker run -it --rm -v "%cd%":/localfile/OpenFPGA -w="/localfile/OpenFPGA" goreganesh/open_fpga bash
|
||||
pause
|
||||
|
|
|
|||
Loading…
Reference in New Issue