diff --git a/.gitignore b/.gitignore index 5651b1ed0..7e355cf96 100644 --- a/.gitignore +++ b/.gitignore @@ -35,4 +35,6 @@ vpr7_x2p/pcre/pcredemo # Some local temporary files .vscode -*_local.bat \ No newline at end of file +*_local.bat +fpga_flow/csv_rpts +tmp/ \ No newline at end of file diff --git a/Dockerfile b/Dockerfile index c573dbbee..7f25b6c01 100755 --- a/Dockerfile +++ b/Dockerfile @@ -1,10 +1,16 @@ -FROM ubuntu:16.04 - -RUN apt-get update -qq -y -RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev - -RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default - -RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA -RUN cd OpenFPGA && make - +FROM ubuntu:16.04 + +RUN apt-get update -qq -y +RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev + +RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default + +RUN mkdir -p /release /dev + +RUN cd release && git clone --single-branch --branch documentation https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA + +RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -CMAKE_BUILD_TYPE=debug && make + +RUN rm -rf /var/lib/apt/lists/* + +WORKDIR /release/OpenFPGA \ No newline at end of file diff --git a/fpga_flow/.gitignore b/fpga_flow/.gitignore new file mode 100644 index 000000000..1a06816d8 --- /dev/null +++ b/fpga_flow/.gitignore @@ -0,0 +1 @@ +results diff --git a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml index bfd21a6d8..f0c7e5752 100644 --- a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +++ b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml @@ -15,7 +15,7 @@ - + @@ -33,7 +33,7 @@ - + @@ -142,7 +142,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -168,7 +168,7 @@ - + @@ -191,7 +191,7 @@ - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + @@ -225,7 +225,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -252,28 +252,8 @@ - - - - @@ -334,14 +314,6 @@ 1 - - @@ -457,12 +429,12 @@ - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 @@ -483,9 +455,8 @@ - - - + + @@ -508,8 +479,8 @@ 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback to get the part that should be marked on the crossbar. --> - - + + diff --git a/fpga_flow/benchmarks/List/lattice_benchmark.txt b/fpga_flow/benchmarks/List/lattice_benchmark.txt index 912818af7..1a5dc6995 100644 --- a/fpga_flow/benchmarks/List/lattice_benchmark.txt +++ b/fpga_flow/benchmarks/List/lattice_benchmark.txt @@ -1,2 +1,6 @@ # Circuit Names, fixed routing channel width, -PID/*.v, 120 \ No newline at end of file +# PID/*.v, 120 +up_counter/*.v, 30 +# MultiBitAdder/*.v, 30 +# i2c_master_top/*.v, 40 +# asynch_fifo/*.v, 30 \ No newline at end of file diff --git a/fpga_flow/configs/lattice_benchmark.conf b/fpga_flow/configs/lattice_benchmark.conf index 7d270f6e3..c74d47581 100644 --- a/fpga_flow/configs/lattice_benchmark.conf +++ b/fpga_flow/configs/lattice_benchmark.conf @@ -1,8 +1,9 @@ # Standard Configuration Example [dir_path] script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example +# yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc @@ -12,7 +13,7 @@ mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results +rpt_dir = /var/tmp/Openfpga/results ace_path = OPENFPGAPATHKEYWORD/ace2/ace [flow_conf] diff --git a/fpga_flow/configs/lattice_benchmark.txt b/fpga_flow/configs/lattice_benchmark.txt new file mode 100644 index 000000000..1a5dc6995 --- /dev/null +++ b/fpga_flow/configs/lattice_benchmark.txt @@ -0,0 +1,6 @@ +# Circuit Names, fixed routing channel width, +# PID/*.v, 120 +up_counter/*.v, 30 +# MultiBitAdder/*.v, 30 +# i2c_master_top/*.v, 40 +# asynch_fifo/*.v, 30 \ No newline at end of file diff --git a/fpga_flow/run_benchmark.sh b/fpga_flow/run_benchmark.sh index c039011b5..41e5ab3f8 100644 --- a/fpga_flow/run_benchmark.sh +++ b/fpga_flow/run_benchmark.sh @@ -4,7 +4,24 @@ set -e # Make sure a clear start default_task='lattice_benchmark' pwd_path="$PWD" -task_name=${1:-$default_task} # run task defined in argument else run default task + +# ========================= Read command argument ========================= +usage() { echo "Usage: $0 [-b ] [-s] run spice only [-p] run vpr only " 1>&2; exit 1; } + +while getopts ":b:vpr:spice:" o; do + case "${o}" in + b) + bench=${OPTARG};; + v) + vpr=1;; + s) + spice=1;; + esac +done +# ========================================================================== + +task_name=${bench:-$default_task} # run task defined in argument else run default task +echo "Running task ${task_name}" config_file="$PWD/configs/${task_name}.conf" bench_txt="$PWD/benchmarks/List/${task_name}.txt" rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv" @@ -16,22 +33,45 @@ config_file_final=$(echo ${config_file/.conf/_final.conf}) # List of argument passed to FPGA flow vpr_config_flags=( - '-N 10' - '-K 6' - '-ace_d 0.5' - '-multi_thread 1' - '-vpr_fpga_x2p_rename_illegal_port' - '-vpr_fpga_verilog' - '-vpr_fpga_bitstream_generator' - '-vpr_fpga_verilog_print_autocheck_top_testbench' - '-vpr_fpga_verilog_include_timing' - '-vpr_fpga_verilog_include_signal_init' - '-vpr_fpga_verilog_formal_verification_top_netlist' - '-fix_route_chan_width' - '-vpr_fpga_verilog_include_icarus_simulator' - '-power' + "-conf ${config_file_final}" + "-benchmark ${bench_txt}" + "-rpt ${rpt_file}" + "-vpr_fpga_verilog_dir ${verilog_path}" + "-N 10" + "-K 6" + "-remove_designs" + "-ace_d 0.5" + "-multi_thread 1" + # "-route_chan_width 10" + "-vpr_fpga_x2p_rename_illegal_port" + "-vpr_fpga_verilog" + "-vpr_fpga_bitstream_generator" + "-vpr_fpga_verilog_print_autocheck_top_testbench" + "-vpr_fpga_verilog_include_timing" + "-vpr_fpga_verilog_include_signal_init" + "-vpr_fpga_verilog_formal_verification_top_netlist" + "-fix_route_chan_width" + # "-vpr_fpga_verilog_include_icarus_simulator" + "-power" + "-vpr_fpga_spice spice_taskfile" + "-vpr_fpga_spice_simulator_path /uusoc/facility/cad_tools/Synopsys/lnis_tools/hspice/P-2019.06/hspice/bin/" + # "-vpr_fpga_spice_print_top_tb" + "-vpr_fpga_spice_print_component_tb", + # "-vpr_fpga_spice_print_grid_tb" +) + +spice_config_flags=( + "-conf /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/vpr_fpga_spice_conf/sample.conf" + "-task /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/scripts/spice_taskfile_yosys_vpr.txt" + "-rpt ${rpt_file/.csv/_spice_result.csv}" + "-multi_thread 10" + # "-parse_grid_tb" + "-parse_pb_mux_tb" + "-parse_cb_mux_tb" + "-parse_sb_mux_tb" + "-parse_lut_tb" + # "-parse_hardlogic_tb" ) -# vpr_config_flags+=("$@") # Append provided arguments #=============== Argument Sanity Check ===================== #Check if script running in correct (OpenFPGA/fpga_flow) folder @@ -63,9 +103,19 @@ sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_f #==================Clean result, change directory and execute =============== cd ${pwd_path}/scripts -# perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -vpr_fpga_verilog_dir $verilog_path $(echo "${vpr_config_flags[@]}") +if [[ -n "$vpr" ]]; then + # Create echo and execute VPR command + command="perl fpga_flow.pl $(echo ${vpr_config_flags[@]})" + echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n" + eval ${command} +fi -perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power +if [[ -n "$spice" ]]; then + # Create echo and SPICE Execution + command="perl run_fpga_spice.pl $(echo ${spice_config_flags[@]})" + echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n" + eval ${command} +fi echo "Netlists successfully generated and simulated" -exit 0 +exit 0 \ No newline at end of file diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index d94d03482..db66be359 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1,4 +1,4 @@ -#!usr/bin/perl -w +#!/usr/bin/perl -w # use the strict mode use strict; # Use the Shell enviornment @@ -1182,6 +1182,7 @@ sub run_odin2($ $ $) { } sub run_pro_blif_3arg($ $ $) { + # Adopt blif format my ($abc_blif_out_bak, $abc_blif_out, $initial_blif) = @_; my ($pro_blif_path) = ($conf_ptr->{dir_path}->{script_base}->{val}); @@ -1301,7 +1302,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) { my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - + my ($power_opts); if ("on" eq $opt_ptr->{power}) { $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; @@ -1460,7 +1461,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) # foreach my $file (0..$#files){ # print "$files[$file]\t"; # } - 3 print "\n"; + # print "\n"; #} chdir $cwd; } @@ -1765,7 +1766,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { print "INFO: try route_chan_width($min_chan_width) success!\n"; last; #Jump out } elsif ($max_route_width_retry < $min_chan_width) { - # I set a threshold of 1000 as it is the limit of VPR + # I set a threshold of 1000 as it is the limit of VPR die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $min_chan_width!\n"; } else { print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; @@ -1791,7 +1792,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { print "INFO: try route_chan_width($fix_chan_width) success!\n"; last; #Jump out } elsif ($max_route_width_retry < $fix_chan_width) { - # I set a threshold of 1000 as it is the limit of VPR + # I set a threshold of 1000 as it is the limit of VPR die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $fix_chan_width!\n"; } else { print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; @@ -2994,11 +2995,11 @@ sub gen_csv_rpt_vtr_flow($ $) my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - # adapt to matlab format if the option is enabled + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3029,7 +3030,7 @@ sub gen_csv_rpt_vtr_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.v$//g; + $tmp =~ s/\.v$//g; print $CSVFH "$tmp"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3078,12 +3079,12 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) my ($tmp,$ikw,$tmpkw); my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled + + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3117,9 +3118,9 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) my @tokens = split('/', $tmp); $tmp = $tokens[0]; - # For matlab script, we use {} for string + # For matlab script, we use {} for string if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "{'$tmp'}"; + print $CSVFH "{'$tmp'}"; } else { print $CSVFH "$tmp"; } @@ -3171,12 +3172,12 @@ sub gen_csv_rpt_standard_flow($ $) my ($tmp,$ikw,$tmpkw); my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled + + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3207,7 +3208,7 @@ sub gen_csv_rpt_standard_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3222,7 +3223,7 @@ sub gen_csv_rpt_standard_flow($ $) @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } if ("on" eq $opt_ptr->{power}) { @@ -3258,11 +3259,11 @@ sub gen_csv_rpt_mpack2_flow($ $) my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - # adapt to matlab format if the option is enabled + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3298,7 +3299,7 @@ sub gen_csv_rpt_mpack2_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; @@ -3353,11 +3354,11 @@ sub gen_csv_rpt_mpack1_flow($ $) my @keywords; my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val}); - # adapt to matlab format if the option is enabled + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3383,7 +3384,7 @@ sub gen_csv_rpt_mpack1_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; #foreach $tmpkw(@keywords) { print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}"; diff --git a/fpga_flow/vpr_fpga_spice_conf/sample.conf b/fpga_flow/vpr_fpga_spice_conf/sample.conf index 92d477f60..e43b53e66 100644 --- a/fpga_flow/vpr_fpga_spice_conf/sample.conf +++ b/fpga_flow/vpr_fpga_spice_conf/sample.conf @@ -12,11 +12,11 @@ hardlogic_tb_dir_name = hardlogic_tb cb_tb_dir_name = cb_tb sb_tb_dir_name = sb_tb # Prefix -top_tb_prefix = +top_tb_prefix = pb_mux_tb_prefix = _grid cb_mux_tb_prefix = _cb sb_mux_tb_prefix = _sb -lut_tb_prefix = _grid +lut_tb_prefix = _grid hardlogic_tb_prefix = _grid grid_tb_prefix = _grid cb_tb_prefix = _cb @@ -34,35 +34,34 @@ sb_tb_postfix = _sb_testbench.sp [task_conf] auto_check = on -num_pb_mux_tb = -num_cb_mux_tb = -num_sb_mux_tb = -num_lut_mux_tb = -num_hardlogic_tb = -num_grid_mux_tb = -num_top_tb = -num_cb_tb = -num_sb_tb = +num_pb_mux_tb = +num_cb_mux_tb = +num_sb_mux_tb = +num_lut_mux_tb = +num_hardlogic_tb = +num_grid_mux_tb = +num_top_tb = +num_cb_tb = +num_sb_tb = [csv_tags] #top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_io|leakage_power_local_interc|total_leakage_power_lut5|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs -top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_local_interc|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs +top_tb_leakage_power_tags = leakage_power_sram_local_routing | leakage_power_sram_luts | leakage_power_sram_cbs | leakage_power_sram_sbs | leakage_power_local_interc | total_leakage_power_lut6 | total_leakage_power_dff | leakage_power_cbs | leakage_power_sbs #top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_io|energy_per_cycle_local_routing|total_energy_per_cycle_lut5|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs -top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs #|crit_path_delay -pb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_pb_mux -cb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_cb_mux -sb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_sb_mux -pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_pb_mux -cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_cb_mux -sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_sb_mux -lut_tb_leakage_power_tags = leakage_power_sram_luts|total_leakage_power_lut6 -lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts|total_energy_per_cycle_lut6 +top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing | energy_per_cycle_sram_luts | energy_per_cycle_sram_cbs | energy_per_cycle_sram_sbs | energy_per_cycle_local_routing | total_energy_per_cycle_lut6 | total_energy_per_cycle_dff | energy_per_cycle_cbs | energy_per_cycle_sbs #|crit_path_delay +pb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_pb_mux +cb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_cb_mux +sb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_sb_mux +pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_pb_mux +cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_cb_mux +sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_sb_mux +lut_tb_leakage_power_tags = leakage_power_sram_luts | total_leakage_power_lut6 +lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts | total_energy_per_cycle_lut6 hardlogic_tb_leakage_power_tags = total_leakage_power_dff hardlogic_tb_dynamic_power_tags = total_energy_per_cycle_dff -grid_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_local_routing|total_leakage_power_lut6|total_leakage_power_dff -grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing|total_energy_per_cycle_sram_luts|total_energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff -cb_tb_leakage_power_tags = leakage_power_cb|leakage_power_sram_cb -cb_tb_dynamic_power_tags = energy_per_cycle_cb|energy_per_cycle_sram_cb -sb_tb_leakage_power_tags = leakage_power_sb|leakage_power_sram_sb -sb_tb_dynamic_power_tags = energy_per_cycle_sb|energy_per_cycle_sram_sb - +grid_tb_leakage_power_tags = leakage_power_sram_local_routing | leakage_power_sram_luts | leakage_power_local_routing | total_leakage_power_lut6 | total_leakage_power_dff +grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing | total_energy_per_cycle_sram_luts | total_energy_per_cycle_local_routing | total_energy_per_cycle_lut6 | total_energy_per_cycle_dff +cb_tb_leakage_power_tags = leakage_power_cb | leakage_power_sram_cb +cb_tb_dynamic_power_tags = energy_per_cycle_cb | energy_per_cycle_sram_cb +sb_tb_leakage_power_tags = leakage_power_sb | leakage_power_sram_sb +sb_tb_dynamic_power_tags = energy_per_cycle_sb | energy_per_cycle_sram_sb diff --git a/run_local.bat b/run_local.bat index 578f750ce..79c20324a 100755 --- a/run_local.bat +++ b/run_local.bat @@ -1,2 +1,2 @@ -docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh +docker run -it --rm -v "%cd%":/localfile/OpenFPGA -w="/localfile/OpenFPGA" goreganesh/open_fpga bash pause