tangxifan
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78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
AurelienUoU
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1a5c5ff4a6
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Update demo simulation result path
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2019-07-12 16:52:54 -06:00 |
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AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
|
AurelienUoU
|
ef600bc63f
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Save workspace
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2019-07-12 15:57:41 -06:00 |
|
AurelienUoU
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d10cc34c9e
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Update Readme and tutorial
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2019-07-12 14:56:08 -06:00 |
Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
|
Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
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tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
|
AurelienUoU
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e65cf9f5fd
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Update ERI-demo
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2019-07-12 08:55:19 -06:00 |
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Baudouin Chauviere
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40d3460bac
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
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29ffa1cdcb
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:09 -06:00 |
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Baudouin Chauviere
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e461cd0b99
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 22:09:49 -06:00 |
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Baudouin Chauviere
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1431ee2f82
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Fix Explicit verilog
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2019-07-11 22:09:34 -06:00 |
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tangxifan
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cffdebd912
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bug fixed for the tileable RR graph generator for heterogeneous blocks
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2019-07-11 21:02:09 -06:00 |
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tangxifan
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75ff2e904e
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 19:41:24 -06:00 |
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tangxifan
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e633e3d17b
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update fpga_flow scripts to support vpr_only flow
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2019-07-11 19:40:58 -06:00 |
|
Baudouin Chauviere
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c9b84f61c9
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Hot fix
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2019-07-11 17:39:02 -06:00 |
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Baudouin Chauviere
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d0cd5a2bc1
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Hot fix
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2019-07-11 17:27:31 -06:00 |
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tangxifan
|
9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
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AurelienUoU
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1848771e54
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Add explicit mapping option into fpga_flow
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2019-07-11 14:44:30 -06:00 |
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Baudouin Chauviere
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f4be375637
|
Latest version explicit
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2019-07-11 14:33:56 -06:00 |
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AurelienUoU
|
ad0b4b3acd
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Merge remote-tracking branch 'origin/dev' into documentation
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2019-07-11 10:15:26 -06:00 |
|
AurelienUoU
|
346b6f3e8e
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Update docker part in building.md
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2019-07-11 10:13:55 -06:00 |
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AurelienUoU
|
c556b85d66
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Update docker instruction
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2019-07-11 10:10:30 -06:00 |
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tangxifan
|
31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
|
AurelienUoU
|
3cd214ada2
|
tuto flow v2.1
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2019-07-10 16:14:38 -06:00 |
|
AurelienUoU
|
db9c4be963
|
Tuto flow v2
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2019-07-10 16:00:22 -06:00 |
|
AurelienUoU
|
9d7ae2f6ec
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Update tutorial flow demo draft 6
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2019-07-10 15:42:31 -06:00 |
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tangxifan
|
a90316e9f4
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 15:13:46 -06:00 |
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tangxifan
|
acee0161c7
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Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
|
tangxifan
|
206fc84a0e
|
minor fix in fpga_flow
|
2019-07-10 15:12:51 -06:00 |
|
AurelienUoU
|
a47711203c
|
Tuto update draft 5
|
2019-07-10 14:59:03 -06:00 |
|
Baudouin Chauviere
|
6441f2ebe7
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 14:16:55 -06:00 |
|
Baudouin Chauviere
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0a978db866
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Fix regression test
|
2019-07-10 14:16:34 -06:00 |
|
tangxifan
|
b7f9831bd2
|
add statistics for unique GSBs
|
2019-07-10 13:08:03 -06:00 |
|
AurelienUoU
|
422ede7610
|
Update tutorial draft 4
|
2019-07-10 12:17:07 -06:00 |
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tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 12:05:43 -06:00 |
|
AurelienUoU
|
cb782a0e9f
|
Draft 3
|
2019-07-10 11:00:36 -06:00 |
|
AurelienUoU
|
905293820f
|
Draft2
|
2019-07-10 10:37:05 -06:00 |
|
AurelienUoU
|
20ce020eb6
|
Tutorial rewrite draft 1
|
2019-07-10 10:03:30 -06:00 |
|
tangxifan
|
57ae5dbbec
|
bug fixing for rectangle FPGA sizes
|
2019-07-09 20:47:52 -06:00 |
|
tangxifan
|
edfe3144c3
|
update profiling, found where runtime is lost
|
2019-07-09 20:28:01 -06:00 |
|
tangxifan
|
737cc2874f
|
Merge branch 'tileable_routing' into dev
|
2019-07-09 17:42:44 -06:00 |
|
tangxifan
|
65f696c1d7
|
fix critical bugs in rectangle floorplan
|
2019-07-09 17:41:20 -06:00 |
|
Baudouin Chauviere
|
4ca0967453
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-09 14:35:51 -06:00 |
|
Baudouin Chauviere
|
792ba23f4f
|
Correction pre-merge
|
2019-07-09 14:34:34 -06:00 |
|
AurelienUoU
|
e86c9b9bfc
|
Update tutorial, readme and docker
|
2019-07-09 14:28:14 -06:00 |
|
AurelienUoU
|
0da9e50b20
|
Modify readme
|
2019-07-09 11:58:39 -06:00 |
|
Baudouin Chauviere
|
589f58b55e
|
Regression test succeeded
|
2019-07-09 09:18:06 -06:00 |
|
Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |