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OpenFPGA
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Update tutorial flow demo draft 6

This commit is contained in:
AurelienUoU 2019-07-10 15:42:31 -06:00
parent a47711203c
commit 9d7ae2f6ec
4 changed files with 6 additions and 5 deletions
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2
README.md
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@ -14,7 +14,7 @@ Dependancies and help using docker can be found at **./tutorials/building.md**.
**Compilation steps:**
1. Create a folder named build in OpenPFGA repository (mkdir build && cd build)
2. Create Makefile in this folder using cmake (cmake ..)
2. Create Makefile in this folder using cmake (cmake .. -DCMAKE_BUILD_TYPE=debug)
3. Compile the tool and its dependencies (make)
*We currently implemented OpenFPGA for:*

2
fpga_flow/scripts/fpga_flow.pl
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@ -1790,7 +1790,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) {
my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width});
# Remove previous route results
if (-e $vpr_route) {
system(rm $vpr_route);
system("rm $vpr_route");
}
# Keep increase min_chan_width until route success
&run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file);

5
fpga_flow/tuto_fpga_flow.sh
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@ -12,7 +12,7 @@ architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml"
architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml"
ff_keyword="FFPATHKEYWORD"
ff_path="${pwd_path}/vpr7_x2p/vpr/Verilognetlists/ff.v"
ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v"
dir_keyword="GENERATED_DIR_KEYWORD"
rm -rf ${pwd_path}/results_OpenPithon
@ -22,11 +22,12 @@ cd ${pwd_path}/scripts
perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file
perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file
perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file
echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path"
perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file
# SRAM FPGA
# TT case
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_verilog_print_modelsim_autodeck $modelsim_ini_path -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test
echo "Netlists successfully generated and tested"

2
tutorials/building.md
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@ -48,5 +48,5 @@ If all these dependancies are not installed in your machine you can choose to us
To build the tool you have to be in OpenFPGA folder and do:
- mkdir build && cd build
- cmake ..
- cmake .. -DCMAKE_BUILD_TYPE=debug
- make OR make -j