riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Tuto update draft 5

This commit is contained in:
AurelienUoU 2019-07-10 14:59:03 -06:00
parent 422ede7610
commit a47711203c
4 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
View File

@ -150,7 +150,7 @@
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0" tileable_routing="on"/>
<layout auto="1.0" tileable_routing="off"/>
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>

34
fpga_flow/configs/tutorial/tuto.conf
View File

@ -1,27 +1,27 @@
# Standard Configuration Example
[dir_path]
script_base = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys
odin2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys-abc
abc_mccl_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/results_tutorial
ace_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/ace2/ace
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
ace_path = OPENFPGAPATHKEYWORD/ace2/ace
[flow_conf]
flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
vpr_arch = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:

2
fpga_flow/tuto_fpga_flow.sh
View File

@ -27,6 +27,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the
# SRAM FPGA
# TT case
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -end_flow_with_test
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_verilog_print_modelsim_autodeck $modelsim_ini_path -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test
echo "Netlists successfully generated and tested"

10
tutorials/fpga_flow/folder_organization.md
View File

@ -1,11 +1,11 @@
# fpga_flow folder organization
The fpga_flow folder is organized as follow:
* [**arch**]: contains architectures description files
* [**benchmarks**]: contains Verilog and blif benchmarks + lists
* [**configs**]: contains configuration files to run fpga_flow.pl
* [**scripts**]: contains all the scripts required to run the flow
* [**tech**]: contains xml tech files for power estimation
* **arch**: contains architectures description files
* **benchmarks**: contains Verilog and blif benchmarks + lists
* **configs**: contains configuration files to run fpga_flow.pl
* **scripts**: contains all the scripts required to run the flow
* **tech**: contains xml tech files for power estimation
## arch
In this folder are saved the architecture files. These files are Hardware description for the FPGA written in XML. This folder contains 3 sub-folders: