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# Standard Configuration Example
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[dir_path]
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script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
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benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
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yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
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odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
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cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
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abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
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abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
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abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
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mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
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m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
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mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
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vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
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rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
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ace_path = OPENFPGAPATHKEYWORD/ace2/ace
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script_base = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/scripts/
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benchmark_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
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yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys
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odin2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
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cirkit_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/cirkit
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abc_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys-abc
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abc_mccl_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc
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abc_with_bb_support_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc
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mpack1_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack1
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m2net_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/m2net
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mpack2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack2
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vpr_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/vpr
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rpt_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/results_tutorial
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ace_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/ace2/ace
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[flow_conf]
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flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
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vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
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vpr_arch = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
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mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
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m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
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m2net_conf = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
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mpack2_arch = K6_pattern7_I24.arch
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power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
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power_tech_xml = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
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[csv_tags]
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mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
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@ -7,8 +7,9 @@ task_name="tuto"
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config_file="$pwd_path/configs/tutorial/${task_name}.conf"
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bench_txt="$pwd_path/benchmarks/List/tuto_benchmark.txt"
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rpt_file="$pwd_path/csv_rpts/fpga_spice/${task_name}.csv"
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verilog_path="${pwd_path}/${task_name}_Verilog"
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architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml"
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architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml"
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ff_keyword="FFPATHKEYWORD"
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ff_path="${pwd_path}/vpr7_x2p/vpr/Verilognetlists/ff.v"
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@ -7,11 +7,13 @@ During this tutorial we consider the user start in the OpenFPGA folder and we'll
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A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh.
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**Experiment**<br />
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### Experiment
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cd fpga_flow<br />
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./tuto_fpga_flow.sh<br />
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**Explanation**<br />
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### Explanation
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By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.<br />
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When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.<br />
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The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md)
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@ -6,8 +6,9 @@ Mandatory options: <br />
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- -benchmark <file> : *the configuration file contains benchmark file names*
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- -rpt <file> : *CSV file consists of data*
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- -N <int> : *N-LUT/Matrix*
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Other Options:<br />
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## General
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## Other Options:
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### General
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- -matlab_rpt <data_name> : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script*
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- -I <int> : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen*
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- -K <int> : *K-LUT, mandatory when standard flow is chosen*
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@ -20,17 +21,17 @@ Other Options:<br />
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- -parse_results_only : *only parse the flow results and write CSV report.*
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- -debug : *debug mode*
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- -help : *print usage*
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## ODIN II
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### ODIN II
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- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)*
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- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen*
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- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow *
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## ABC
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### ABC
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- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.*
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- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.*
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## ACE
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### ACE
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- -ace_p <float> : *specify the default signal probablity of PIs in ACE2.*
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- -ace_d <float> : *specify the default signal density of PIs in ACE2.*
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## VPR - Original Version
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### VPR - Original Version
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- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.*
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- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.*
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- -vpr_max_router_iteration <int> : *specify the max router iteration in VPR.*
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@ -38,12 +39,12 @@ Other Options:<br />
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- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.*
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- -min_route_chan_width <float> : *turn on routing with <float>* min_route_chan_width.*
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- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.*
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## VPR - FPGA-X2P Extension
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### VPR - FPGA-X2P Extension
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- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE*
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- -vpr_fpga_x2p_signal_density_weight <float>: *specify the option signal_density_weight of VPR FPGA SPICE*
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- -vpr_fpga_x2p_sim_window_size <float>: *specify the option sim_window_size of VPR FPGA SPICE*
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- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization*
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## VPR - FPGA-SPICE Extension
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### VPR - FPGA-SPICE Extension
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- -vpr_fpga_spice <task_file> : *turn on SPICE netlists print-out in VPR, specify a task file*
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- -vpr_fpga_spice_sim_mt_num <int>: *specify the option sim_mt_num of VPR FPGA SPICE*
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- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE*
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- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE*
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- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE*
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- -vpr_fpga_spice_simulator_path <string> : *Specify simulator path*
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## VPR - FPGA-Verilog Extension
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### VPR - FPGA-Verilog Extension
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- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_dir <verilog_path>: *provides the path where generated verilog files will be written*
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- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files*
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- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: *turn on printing modelsim simulation script*
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## VPR - FPGA-Bitstream Extension
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### VPR - FPGA-Bitstream Extension
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- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator*
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